Data relay controller

Details Data relay controller Data relay controller

2006-08-08

2006-08-08

Lane, Jack (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S004000, C711S111000, C711S219000, C709S241000, C709S241000, C709S241000

Reexamination Certificate

active

07089401

ABSTRACT:
A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.

REFERENCES:
patent: 4866717 (1989-09-01), Murai et al.
patent: 5109500 (1992-04-01), Iseki et al.
patent: 5523799 (1996-06-01), Hattori et al.
patent: 5-40604 (1993-02-01), None

Affiliated with

Also associated with

Rating

Data relay controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data relay controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data relay controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3632770