Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2002-04-26
2004-06-01
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S080000
Reexamination Certificate
active
06744279
ABSTRACT:
The invention relates to a data register for storage of a data bit with integrated signal level conversion.
In many applications, it is necessary to store a data bit, which originates from a data source, in a data register or in a buffer store, and to carry out voltage level conversion for further data processing. The reason for this is that, because of the technology, the data source in many cases operates with a different signal level shift than a downstream data processing circuit.
FIG. 1
a
shows an arrangement according to the prior art. A data source which is supplied with a first supply voltage v
1
generates data which is written to a data register. Signal matching is carried out in a downstream level converter circuit by raising or lowering the voltage shift of the signal, and the matched signal is supplied to the data processing unit, which is supplied with a second supply voltage v
2
.
FIG. 1
b
shows a further arrangement according to the prior art, in which signal matching is first of all carried out by signal level conversion, and the already matched signal is then buffer-stored in a data register for further data processing.
By way of example,
FIG. 2
shows the circuitry design of the arrangement according to the prior art illustrated in
FIG. 1
a
. The data register has a controllable switching device which comprises two complementary field-effect transistors T
1
, T
2
, with a control signal S and a control signal {overscore (s)}, which is inverted with respect to the control signal S, driving the gate connections of the two field-effect transistors. In the example illustrated in
FIG. 2
, an NMOS transistor is driven by a control signal s, and a PMOS transistor, which is complementary to it, receives the inverted control signal {overscore (s)}. If the control signal s is a logic high, the data signal which is applied to the data input E and originates from the data source is passed on to the input of an inverter stage.
The first inverter stage, which comprises the complementary field-effect transistors T
5
, T
6
, of the data register couples the applied data bit, in inverted form, to a second inverter stage
0
, which, in the example illustrated in
FIG. 2
, comprises the field-effect transistors T
3
, T
4
. The feedback or latching results in the data bit that has been read being held or buffer-stored in the data register. The data register, together with its two inverter stages, is supplied with a first supply voltage v
1
.
In order to increase the voltage level shift, the data register output side is connected to a signal level converter. The signal level converter contains a potential isolating transistor T
7
, whose gate is connected to the first supply voltage. Furthermore, the signal level converter contains an inverter stage which comprises two complementary field-effect transistors T
9
, T
10
, which feeds back the applied data signal, in the inverted form, via a feedback transistor T
8
. The feedback transistor T
8
is connected to a second supply voltage v
2
. The first supply voltage v
1
is lower than the second supply voltage v
2
, with, for example, the first supply voltage being 1.8 volts, and the second supply voltage being 3.3 volts. The feedback results in the voltage level being increased, and the data signal D is emitted with an increased voltage shift to the downstream data processing unit for further data processing.
The circuit arrangement according to the prior art has the disadvantage that the circuit arrangement comprises two circuit modules, namely a data register on the one hand and a level converter on the other hand. A relatively large number of transistors T
1
to T
10
are thus required in order to buffer-store a data bit and to carry out signal level matching. Furthermore, the signal delay times are relatively long, because the data register and the level converter are connected in series.
The object of the present invention is thus to provide a data register which, in addition to buffer storage of the data bit, also carries out signal level conversion, with little circuitry complexity.
The invention provides a data register for storage of a data bit with integrated signal level conversion, having an input for application of a data input signal which has a first signal voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit input signal, a potential isolating transistor whose control connection is at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data input bit signal as a data output signal which has a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for buffer storage of the data bit signal.
One advantage of this data register according to the invention is that the signal delay time between the input of the data register and the output of the data register is short, so that a data bit which originates from a data source is passed with a short delay time and at the necessary voltage level for further data processing to a downstream data processing unit.
In one preferred embodiment of the data register according to the invention, the first voltage potential v
1
is lower than the second voltage potential v
2
.
The second inverter is preferably supplied with the first voltage potential v
1
, and the data output signal is fed back to a first potential node between the controllable switching device and the potential isolating transistor.
In one preferred embodiment, the first inverter and the second inverter each contain a PMOS and an NMOS field-effect transistor.
The isolating transistor is preferably an NMOS field-effect transistor.
In one preferred embodiment of the data register according to the invention, a feedback transistor is provided, which feeds back the data output signal to the gate connection of the PMOS field-effect transistor in the first inverter. The feedback transistor is preferably a PMOS field-effect transistor.
In a further embodiment of the data register according to the invention, the second inverter is supplied with the second voltage potential, and the data output signal is fed back to a second potential node between the potential isolating transistor and the first inverter.
In one preferred embodiment, the first potential node is connected to the gate connection of the NMOS field-effect transistor in the first inverter.
The controllable switching device for the data register according to the invention has, in one preferred embodiment, a PMOS field-effect transistor and an NMOS field-effect transistor.
REFERENCES:
patent: 4612659 (1986-09-01), Starke
patent: 5949721 (1999-09-01), Kwon et al.
patent: 6005432 (1999-12-01), Guo et al.
patent: 19738726 (1998-07-01), None
Chrissotomidis Ioannis
Fischer Helmut
Greenblum & Bernstein P.L.C.
Infineon - Technologies AG
Tran Anh
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