Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-06-12
2000-10-24
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711167, 711154, G06F 1314
Patent
active
06138206&
ABSTRACT:
A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses and for responding to slot MRU misses and cache misses. An N-way set associative cache is provided, each set of said cache including an SRAM array macro having a memory element, an internal SRAM data register, and a read enable signal line. Read enable is generated as the NOR of slot miss and cache miss signals, and the internal SRAM data register is responsive to the slot miss signal for registering data output during a first cycle for use in a next following cycle.
REFERENCES:
patent: 5228134 (1993-07-01), MacWilliams et al.
patent: 5287481 (1994-02-01), Lin
patent: 5392410 (1995-02-01), Liu
patent: 5392414 (1995-02-01), Yung
patent: 5414827 (1995-05-01), Lin
patent: 5418922 (1995-05-01), Liu
patent: 5450565 (1995-09-01), Nadir
patent: 5463759 (1995-10-01), Ghosh et al.
patent: 5488709 (1996-01-01), Chan
patent: 5822756 (1998-10-01), Thome et al.
patent: 5845323 (1998-12-01), Roberts et al.
Handy, J., "The Cache Memory Book", ISBN0-12-322985-5, (C) 1993, pp. 101-102.
"Pipelined Cache Dedsign for High Reliability", IBM Technical Disclosure Bulletin, vol. 37, No. 07, Jul. 1994 pp. 73-79.
"Cache Optimized Structure Supporting Global Object Locks", IBM Technical Disclosure Bulletin, vol. 37, No. 06B, Jun. 1994, pp. 11-17.
"Cache Memory Stgructure for Tolerating Faults", IBM Technical Disclosure Bulletin, vol. 38, No. 05, May 1995, pp. 589-590.
Seznec, A. "DASC Cache", Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture, Jan. 1995, INSPEC, INSM Abstract An 4881204.
Farkas, K.I. et al. "How Useful . . . ", Proceedings First IEEE Symposium on High-Performance Computer Architecture. Feb. 1995. INSPEC abstract AN4881199.
Bost, E. et al. "A 64-bit Supercomputer on a Single Chip", Electron, No. 169, pp. 29-32, Jan. 22, 1990; INSPEC abstract AN B90049244.
Fisher Michael Todd
Gilda Glenn David
Beckstrand Shelly M.
Cabeca John W.
Chow Christopher S.
International Business Machines - Corporation
LandOfFree
Data register for multicycle data cache read does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data register for multicycle data cache read, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data register for multicycle data cache read will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1975705