Data reduction using rank-of-ranks methodology

Details Data reduction using rank-of-ranks methodology Data reduction using rank-of-ranks methodology

1999-06-21

2002-05-07

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06385762

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of data reduction, and more particularly to data reduction using a data analysis methodology.
BACKGROUND OF RELATED ART
The fabrication of printed circuit (PC) boards and related electrical equipment requires the diagnostic testing of performance factors or parameters including voltage and signal deviations, jitters, voltage rise and fall time and other signal integrity factors. The testing of these parameters helps identify anomalous data points from which a problem or failure in the PC board can be determined. Known testing methods of signal integrity in the manufacture of PC boards includes identifying probe or node points from a schematic or CAD layout of the PC board. These node points are located throughout the entire PC board in areas surrounding components, drivers, voltage points and the like and represent points of contact on the PC board.
The number of node points incorporated throughout a PC board can be large; consequently, raising the level of complexity required to perform any type of statistical or data related analysis of the testing results (raw data) obtained from the PC board. Additionally, these results include varied unit designations, such as, voltage, amperage, inductance, capacitance and time readings which further complicate data analysis of the results obtained from the diagnostic testing of the node points.
Once the node points of the PC board are tested and the results (raw data) are obtained, statistical analysis of the data is required in order to ascertain any problem or anomalous data which may indicate problem or defective areas in the PC board. Further, the large amounts of raw data often must be statistically processed in order to emphasize a small subset of data that may be useful to engineering personnel using the data to assess behavioral characteristics of circuitry on the PC board. To this end, there are many methods of performing statistical analysis on data including multiple regression and factor analysis. In using multiple regression, see, for example, Engineering Statistics by Douglas C. Montgomery et al., no ideal data model can be extrapolated due to the varied units which prevents quantitative aggregation of the raw data in a useful model form. The use of other known statistical factor analysis methods presents similar problems in consistently presenting guidelines for discerning problems at the node points.
SUMMARY
The present invention provides a method and apparatus for performing data reduction to results of diagnostic testing of signal integrity of PC boards using a Rank-of-Ranks data analysis methodology. Raw data obtained from the diagnostic testing of signal integrity at node points situated on PC boards is manipulated to a succinct form using the Rank-of-Ranks data analysis methodology.
According to the invention, the Rank-of-Ranks methodology includes an initial reduction of the quantity of analyzed node points on a PC board, by application of a node point reduction algorithm or selection criterion. The remaining node points to be tested (“the test nodes”), each are identified by a node name and associated node position in (x-y-z) coordinate system. The test nodes are physically tested via a testing probe positioned on the end of a robot which moves along the node position coordinates. The testing at each node point includes sample measurements of selected testing parameters or factors. Standard Deviations and Mean are calculated for each selected testing parameter. All test data is compiled at a server and input into a spreadsheet for data manipulation using the Rank-of-Ranks methodology.
Data manipulation using the Rank-of-Ranks methodology according to the present invention includes calculating a Coefficient of Variation as a ratio of the Standard Deviation of a given factor, to the Mean, for each node point (and for each parameter). Each node point is sorted and ranked based on the Coefficient of Variation for each parameter at a time. At each node point, Rank values of all the parameters are summed and then sorted on the basis of the Rank values. Finally, the node points are Re-ranked based on the sorted Rank values. The Re-ranked node points are entered into an ordered list or matrix where critical node points are chosen from the top of the Re-ranked node points for study, re-design and/or further testing of the PC board.
Advantages of the present invention include reduction of node points involved in the testing of PC boards which allow the testing procedures to be more focused and to require less time thereby greatly increasing productivity and lowering manufacturing costs. Also, diagnostic testing of the PC boards can be targeted to include certain critical and control state node points.


REFERENCES:
patent: 6151582 (2000-11-01), Huang
patent: 6223332 (2001-04-01), Scepanovic
“Building Empirical Models”, Chapter 6, pp. 275-293.

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