Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-02-25
2004-04-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S185090
Reexamination Certificate
active
06728913
ABSTRACT:
BACKGROUND
A flash cell can be a field effect transistor (FET) including a select gate, a floating gate, a drain, and a source. A cell can be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to select gate, the cell can be switched on and off.
Flash memory cells can be grouped into NAND type and NOR type circuits. NAND flash memory cells have an n cell transistors connected in series and are connected in parallel between bit lines and ground lines. NAND flash memory cells are useful in large scale integration. NOR flash memory cells include cell transistors that are connected in parallel between bit lines and ground lines. NOR flash memory cells provide high-speed operation.
Programming a cell includes trapping excess electrons in the floating gate to increase voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed when the cell current is less than a reference current and the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied.
Existing memory refresh circuits refresh data on a cell by cell basis or a time basis, such as hourly. Refreshing the data takes time and may not be necessary every hour, day, etc.
BRIEF SUMMARY
A method of programming a memory device having a plurality of pages of memory. The method includes programming the memory, monitoring the memory for defects, creating a copy of the data, erasing the old version of the data, and rewriting the data. The first page of memory is programmed with a first data set. The first page of memory is monitored for errors. During the monitoring for errors, some detected errors may be corrected. When the number of errors detected exceeds a threshold, a copy of that page of is created. The number of errors detected can be a fixed number a percentage of the memory, or time dependent. The copy can be created in an other page of local memory of in remote memory. Then the first page of memory is erased. Finally, the first data set rewritten.
REFERENCES:
patent: 4493081 (1985-01-01), Schmidt
patent: 4612640 (1986-09-01), Mehrotra et al.
patent: 4958350 (1990-09-01), Worley, III et al.
patent: 5450424 (1995-09-01), Okugaki et al.
patent: 5532962 (1996-07-01), Auclair et al.
patent: 5546402 (1996-08-01), Niijima et al.
patent: 5606532 (1997-02-01), Lambrache et al.
patent: 5956352 (1999-09-01), Tatosian et al.
patent: 6002612 (1999-12-01), Noda et al.
patent: 6058046 (2000-05-01), Imamiya et al.
patent: 6058047 (2000-05-01), Kikuchi
Choi et al., A High Speed Programming Scheme for Multi-Level NAND Flash Memory, 1996, IEEE< p. 170-171.
Advanced Micro Devices , Inc.
Chase Shelly A
De'cady Albert
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