Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-12-08
2001-12-18
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C360S045000, C360S065000
Reexamination Certificate
active
06332205
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data recovery systems and more particularly to systems utilizing partial response maximum-likelihood (PRML) detection.
Data recovery systems are used in a variety of applications. In one application, such system is used to recover (i.e., read) data stored on a magnetic disk of the type used as hard drives in computer data storage systems. In one type of such data storage system, a predetermined preamble pattern is written onto the magnetic disk before the start of any block of data to be stored. The preamble pattern is used during the read operation to acquire initial gain, frequency and phase lock to the data read from the disk. Thus, when data is read from the disk, the preamble is used by the read channel during a preamble recovery mode to obtain clock (i.e., sampling or timing) pulses for a subsequent data recovery mode.
The data read from the magnetic disk is passed through an analog equalization filter prior to passing to succeeding stages of the data recovery system. The analog equalization filter is configured to shape the sequence of preamble pulses and data pulses into pulses having a predetermined waveform characteristic. The analog equalization filter has a non-linear change in phase as a function of frequency characteristic. The analog equalization filter produces pulses that are fed to an analog to digital converter. The analog-to-digital converter converts samples of the shaped pulses into corresponding digital words in response to the clock pulses (i.e., sampling pulses) fed to a clock input of the converter. One such arrangement is shown in U.S. Pat. No. 5,220,466.
Direct current (DC) offsets may be introduced into the data recovery process by analog signal processing circuitry, such as amplifiers and filters. The DC offsets of theses devices may vary as a function of temperature and signal gain. The DC offset associated with these non-ideal devices results in a signal level shift which, if uncorrected can degrade performance of the data recovery system. One technique suggested to compensate for this DC offset is discussed in U.S. Pat. No. 5,459,679.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, a data recovery system is provided. The data is represented by a sequence of data pulses comprising a predetermined sequence of preamble pulses fed to the system during a preamble acquisition mode followed by the sequence of data pulses fed to the system during a subsequent data recovery mode. The data pulses have desired data pulses and a DC offset component. The system includes a negative feedback loop, having a differencing network fed by the data pulses and a feedback signal representative of the DC offset component. The differencing network removes the DC offset component in response to only actual values of data pulses fed thereto during the preamble acquisition mode and in response to both actual data pulses and estimated values of such data pulses fed thereto during the data recovery mode.
In accordance with another feature of the invention, a data recovery system is provided wherein the data is represented by a sequence of pulses comprising a predetermined sequence of preamble pulses fed to the system during a preamble acquisition mode followed by the sequence of data pulses fed to the system during a subsequent data recovery mode. The data pulses have desired data pulses and a time varying DC offset component. Each one of such data pulses during the preamble acquisition mode has a predetermined period, 4T. The system includes a source of clock pulses produced at a predetermined rate, R, where R=1/T. A negative feedback loop is provided for cancelling the DC offset component. The negative feedback loop includes a differencing network fed by the data pulses and a feedback signal representative of the DC offset component. The differencing network removes the DC offset component from the data pulses fed thereto to produce a difference signal representative of the desired data pulses. The feedback loop includes an analog to digital converter fed by the output signal and the clock pulses for converting samples of such output signals into corresponding digital words in response to the clock pulses. An integrator is fed by the digital words converted by the analog to digital converter and by the clock pulses for cumulating algebraically adding the digital words fed thereto in response to the clock pulses. A gate is provided for selectively successively coupling to an output of the gate each Nth digital word fed to such gate by the integrator, where N is an integer greater than one. The gate inhibits from such output other ones of the digital words. A digital to analog converter is fed by the digital words coupled to the output of the gate for converting such digital words into a corresponding analog signal to provide the feedback signal for the differencing network.
REFERENCES:
patent: 5459679 (1995-10-01), Ziperovich
patent: 5583706 (1996-12-01), Dudley et al.
patent: 5828476 (1998-10-01), Bonebright et al.
patent: 5991107 (1999-11-01), Behrens et al.
“A CMOS 260Mbps Read Channel with EPRML Performance”, Thomas Conway et al., Analog Devices, pp. 1-4.
Jorgenson Lisa K.
Morris James H.
STMicroelectronics N.V.
Tu Christine T.
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