Data recorder and data producing circuit

Details Data recorder and data producing circuit Data recorder and data producing circuit

1999-01-29

2001-08-14

Shin, Christopher B. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C710S065000, C369S059160

Reexamination Certificate

active

06275878

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a data recorder for use in an apparatus which writes data into a record medium such as a DVD-RAM, and a data producing circuit incorporated into the data recorder.
A conventional data recorder will be described with reference to FIG.
14
. The conventional data recorder includes a microcomputer
1
for controlling the system, a first encoder
3
for applying a first encoding processing operation to input data
2
which is to be recorded onto a record medium
24
for temporary storage in a memory
10
and being activated by a first activation signal
4
, a second encoder
11
for reading first data
7
which is temporarily stored in the memory
10
, applying a second encoding processing operation to the data before it is temporarily stored again in the memory
10
, and being activated by a second activation signal
12
, and a data reader
16
which sends data
20
read out from the memory
10
to a data transducer
23
. A first enable signal
5
is used in switching a region in the memory
10
which is accessed by the first encoder
3
. The first data
7
from the first encoder
3
is stored in a region in the memory
10
which is specified by a first address
6
. A region in the memory
10
which is accessed is specified by a selection address
8
, and a read/write operation of selected data
9
is performed in the region. A second enable signal
13
switches a region within the memory
10
as it is accessed by the second encoder
11
. Data from the second encoder
11
is stored in the memory
10
in a region specified by a second address
14
. The second data
15
is transferred between the memory
10
and the second encoder
11
as a result of read/write operation.
A region in the memory
10
is switched by a third enable signal
18
as it is accessed by the data reader
16
, and third data
20
is read out by the data reader
16
from a memory region specified by a third address
19
. The data reader
16
provides data output
21
, which is written into a record medium
24
by a data transducer
23
. The microcomputer
1
sends an encoding initiate signal
22
to a sync signal set-up section
29
and to a first encoding activation section
30
. In response to the initiate signal
22
which is input from the microcomputer
1
, the sync signal set-up section
29
produces a second sync signal
26
which has a period that is sixteen times the period of a first sync signal
25
and which is synchronized with the first sync signal
25
. The first sync signal
25
is produced by a sync detector
27
when it has detected sector information from the record medium
24
.
The microcomputer
1
also sends an initialize signal
28
which initializes a region in the memory
10
as the first encoder
3
, the second encoder
11
and the data reader
16
accesses the region in the memory
10
. The first encoding activation section
30
produces a first activation signal
4
and a first enable signal
5
when the encoding initiate signal
22
and the second sync signal are input thereto. A second encoding activation section
32
produces a second activation signal
12
and a second enable signal
13
when an end of the first encoding signal
31
is input thereto.
The first encoder
3
is activated when the first activation signal
4
and the second sync signal
26
are input thereto. A block in the memory
10
which is accessed is changed to a next block when the first enable signal
5
and the second sync signal
26
are input. Similarly, the second encoder
11
is activated when the second activation signal
12
and the second sync signal
26
are input thereto, and a block in the memory
10
which is accessed is changed to a next block when the second enable signal
13
and the second sync signal
26
are input. A block in the memory
10
which is accessed by the data reader
16
is also changed to a next block when the third enable signal
18
and the second sync signal
26
are input.
FIG. 13
shows a data structure written into the record medium
24
.
FIG. 15
shows a logical construction of the overall record medium
24
including a lead-in area
31
, representing a leader portion of a record medium structure
30
, a data area
32
where data is recorded, and a lead-out area
33
, which represents a last portion of the structure. The data area
32
comprises a plurality of sectors, and sixteen sectors define one block.
FIG. 16
shows a physical construction of the record medium
24
. The first sync signal
25
is produced at a period of a sector while the second sync signal
26
is produced at a period of a block. A sector address is recorded in the leading end of each sector.
FIG. 17
shows a correspondence between the memory
10
and the data structure of the record medium
24
. One block in the memory
10
comprises an amount of data corresponding to sixteen sectors. It is to be noted that data is treated in block unit on the memory
10
, but is written into the record medium
24
in sector unit.
Next, the operation of the conventional data recorder will be described. Referring to the figures, the microcomputer
1
outputs the initialize signal
28
so that a region in the memory
10
which is accessed by the first encoder
3
, the second encoder
11
and the data reader
16
is defined as a block #
0
. A signal from the record medium
24
causes the sync detector
27
to produce the first sync signal
25
. The sync signal set-up section
29
produces the second sync signal
26
in synchronism with the first sync signal
25
wherever the encoding initiate signal
22
is input from the microcomputer
1
. The second sync signal
26
represents a leading end of a block which is dealt with in the first and the second encoding operation.
The first encoding activation section
30
outputs the first activation signal
4
which activates the first encoder
3
after the encoding initiate signal
22
has defined the leading end of a block. In response to the first activation signal
4
and the second sync signal
26
, the first encoder
3
executes an encoding processing of the input data
2
for respective sixteen sectors, and outputs the first address
6
and the first data
7
, which results from the encoding processing of input data, for temporary storage of the data in the memory
10
. The first address
6
and the first data
7
are transferred through an address bus and a data bus, respectively, in the form of the selection address
8
and the selected data
9
, whereby the selected data is temporarily stored in the memory
10
at an address accessed by the selection address. Subsequently, the first encoding activation section
30
delivers the first enable signal
5
to change a region to be written from the first encoder to the next block #
1
.
The first encoder
3
then delivers the end of a first encoding signal
31
to the second encoding activation section
32
, which responds thereto by sending the second activation signal
12
which activates the second encoder
11
. The second encoder
11
accesses, by way of the second address
14
, the block #
0
which is selected by the first encoder
3
for temporary storage, reading it out as the second data
15
. A second encoding is applied to the data thus read out for respective blocks, and the data is then again written into the block #
0
in the memory
10
. The second encoding activation section
32
then delivers the second enable signal
13
, which changes a second point of encoding to the block #
1
.
The microcomputer
1
now delivers a third activation signal
17
, whereupon the data reader
16
delivers the third address
19
, which is used to access the memory
10
to read out the data in the block #
0
which is written into by the second encoder
11
as third data
20
. The third data
20
is read out and output on sector basis. The third data
20
on sector basis is transferred as a data output
21
from the data reader
16
to the data transducer
23
, which transduces it into a signal form to be recorded on the record medium
24
. The

Affiliated with

Also associated with

Rating

Data recorder and data producing circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data recorder and data producing circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data recorder and data producing circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2541396