Data receiving apparatus of a PCI express device

Details Data receiving apparatus of a PCI express device Data receiving apparatus of a PCI express device

2005-08-30

2009-11-03

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

C358S426090, C370S333000, C398S009000, C398S027000

Reexamination Certificate

active

07613959

ABSTRACT:
A data receiving apparatus of a PCI Express system includes a receiving device, an 8B10B decoder, a forged packet removing device, and a descrambling circuit. The forged packet removing device determines whether a disparity error occurs; and an offset removing circuit compensates a number of cycles of the lane offset. The data receiving apparatus is capable of eliminating error packet caused by framing error and preventing the problem of symbol disorder and disconnection caused by set ordered noise. Furthermore, the data receiving apparatus is also capable of removing offset.

REFERENCES:
patent: 5574731 (1996-11-01), Qureshi
patent: 6622273 (2003-09-01), Barnes
Altera, 8B10B Encoder/Decoder MegaCore Function User Guide, Dec. 2002, version: 1.3.2 rev1, pp. 1-32.
Altera, PHY Interface for the PCI Express Architecture, Jun. 19, 2003, version 1.0, pp. 1-31.
Intel Corporation, PHY Interface for the PCI Express Architecture, Jun. 19, 2003, version 1.0, pp. 1-31.

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