Data receivers for reproducing data input signals and...

Details Data receivers for reproducing data input signals and... Data receivers for reproducing data input signals and...

2002-02-28

2003-07-08

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S077000, C327S563000

Reexamination Certificate

active

06590429

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of semiconductor devices, and more specifically to data input receivers for receiving and reproducing data signals, and methods for detecting data signals in data input receivers.
2. Description of the Related Art
Semiconductor devices process data that is provided as digital signals. These typically encode information as a “one” (at a high voltage) or a “zero” (at a low voltage).
Semiconductor devices are becoming progressively smaller and faster. The circuits within them are becoming packed more densely, and are spending less power. To accommodate these trends, there is a desire to have signals that carry data change more quickly from representing one value to the next, and to be provided at smaller voltage differences.
Semiconductor devices often pass data signals between each other. A device receives such data signals, and must determine whether each is a zero or a one. This has proven difficult, as data signals become attenuated, and more subject to noise.
Accordingly semiconductor devices now sometimes incorporate a separate component, which is called a data receiver. Other times, data receivers are standalone devices. Data receivers receive such data signals, and determine whether each is a zero or a one.
Data receivers have not been implemented very successfully in the prior art. They solve some of the problems of attenuation and noise, but tend to run into fundamental limits. These are described below.
Referring to
FIG. 1A
, a first data receiver
100
in the prior art is described. The scheme of
FIG. 1A
uses single reference signaling, and is also called pseudo differential.
Receiver
100
receives N data signals DATA
1
, DATA
2
, . . . , DATAN, and a single reference voltage VREF. Each signal is received on a separate line. Therefore the scheme uses N+1 input lines. Receiver
100
detects the voltages on the input lines, and outputs data signals DOUT
1
, DOUT
2
, . . . , DOUTN.
Referring to
FIG. 1B
, each data signal DATAi is a “1” if it is higher than VREF, and a “0” if lower than VREF. Accordingly, a voltage difference DD
1
must be detected.
Referring to
FIG. 1C
, a comparator
130
is shown. Device
100
has at least one such comparator
130
for each received data signal DATAi. Each comparator
130
receives one of the data signals DATAi in the positive terminal, and the reference voltage VREF in the negative terminal. Each comparator
130
then outputs the respective output signal DOUTi. The fundamental limit is whether DD
1
exceeds the noise level.
FIG. 1D
is a timing chart that illustrates design requirements on the incoming data signals. For detection to work well, signal DATAi must have a large swing to exceed the noise level. This means that a “1” must be a voltage higher than a high threshold voltage VIH, and a “0” must be a voltage lower than a low threshold voltage VIL. Otherwise, detection is susceptible to electrical noise.
The device of
FIG. 1A
cannot be used reliably in high speed systems. This is due increased noise, and also due to voltage attenuation through transmission line, as data transmission speed increases.
Referring to
FIG. 2A
, a second data receiver
200
in the prior art is described. The scheme of
FIG. 2A
uses differential signaling, and is also called fully differential.
Receiver
200
receives 2N data signals DATA
1
, /DATA
1
, DATA
2
, /DATA
2
, . . . , DATAN, /DATAN, but no reference voltage. Each data signal is received on a separate line, and therefore the scheme uses 2N input lines. Receiver
200
detects the voltages on the input lines, and outputs data signals DOUT
1
, DOUT
2
, . . . , DOUTN, and also optionally /DOUT
1
, /DOUT
2
, . . . , /DOUTN.
Referring to
FIG. 2B
, each data value is denoted by a pair of signals, working together. A value of “1” is signified by having DATAi be “high” while simultaneously /DATAi is “low”. Each data signal is “0” otherwise. A backslash “/” signifies a complementary signal. Accordingly, data signal /DATAi is also called the complement of data signal DATAi.
Referring to
FIG. 2C
, a comparator
230
is shown. Device
200
has one such comparator
230
for each pair of received data signals DATAi, /DATAi. Each comparator
230
receives one of the data signals DATAi in the positive terminal, and the complementary /DATAi in the negative terminal. Each comparator
230
then outputs the respective output signal DOUTi, and also optionally the complement /DOUTi.
The fundamental limit is whether the comparator input DD
2
exceeds the noise level. Device
200
can tolerate a smaller swing in the voltage of each data signal, since it uses two signals together. Accordingly, it can receive data at a higher speed than device
100
.
Data receiver
200
, however, requires 2N data lines compared to the N+1 of data receiver
100
. This burdens the system, and requires a larger package size, which is contrary to present trends.
Referring to
FIG. 3A
, a third data receiver
300
in the prior art is described, which uses a double reference signaling scheme. Receiver
300
is disclosed in U.S. Pat. No. 6,160,423.
Receiver
300
receives N data signals DATA
1
, DATA
2
, . . . , DATAN, and two reference voltages VTR, /VTR. Each signal is received on a separate line. Therefore the scheme uses N+2 input lines. Receiver
300
detects the voltages on the input lines, and outputs data signals DOUT
1
, DOUT
2
, . . . , DOUTN.
Referring to
FIG. 3B
, the two reference voltages VTR, /VTR are complementary to each other, and oscillate. They toggle, so that they remain complementary.
Referring to
FIG. 3C
, detection circuits
320
,
330
of device
300
are shown. Circuit
320
produces intermediate reference voltages VT, /VT, which are delayed in processing by the amount it takes to process through one comparator and two inverters. This way they are synchronized with signal DOUTi, as will be seen from the below.
Circuit
330
is provided once for each of the input data signals DATAi. Data signal DATAi is compared with VTR, /VTR at comparators
332
,
334
. Outputs from comparators
332
,
334
are passed through switches
342
,
344
, where only one of them is allowed to pass through, and become output voltage signal DOUTi. Switches
342
,
344
are controlled by the outputs of XOR (“exclusive-OR”) gates
352
,
362
, which in turn receive the output voltage DOUTi and one of intermediate reference voltages VT, /VT. Inverters
372
are provided to compensate for the processing time delay of XOR gates
352
,
362
, so that the system is stable.
The fundamental limitation of device
300
is that, for detection to work, the data signal DATAi must be either larger than both VTR and /VTR, or smaller than both of them, at detection time. Otherwise device
300
fails, as shown for the two instances below.
Referring to
FIG. 3D
, a computer simulation is shown, which investigates what happens in device
300
when an even small voltage offset (50 mV) develops between the data signal DATAi and the intermediate reference values VT, /VT. As can be seen, device
300
fails when such develops.
More particularly, the computer simulation of
FIG. 3D
generated an input data signal (top graph) and a resulting output signal (bottom graph). The input data signal changes to assume the input values 01110111. The intermediate reference values VT, /VT take values between 1.20 V and 1.60 V, while DATAi takes values between 1.25 V and 1.65 V. The output voltage DOUTi remains high, without tracking the input values 01110111.
Referring to
FIG. 3E
, another computer simulation is shown, which investigates what happens in device
300
when the data signal DATAi is attenuated to be within the intermediate reference values VT, /VT. As can be seen, device
300
fails when that happens.
More particularly, the computer simulation of
FIG. 3E
generated an input data signal (top graph) and a resulting output signal (bottom graph). The input data signal changes to assume the input values 01110111. The intermediate reference valu

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