Data reading method of ferroelectric memory device, and ferroele

Details Data reading method of ferroelectric memory device, and ferroele Data reading method of ferroelectric memory device, and ferroele

1997-11-18

2000-02-22

Hoang, Huan

Static information storage and retrieval

Systems using particular element

Ferroelectric

365149, G11C 1122

Patent

active

060287829

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a reading method of ferroelectric memory device, and a ferroelectric memory device.


BACKGROUND ART

Recently, by using a ferroelectric material in the capacitor of memory cell, a ferroelectric memory device realizing nonvolatility of stored data is devised. The ferroelectric capacitor has a hysteresis characteristic, and if the electric field is zero, a residual polarization of different polarity depending on the hysteresis is left over. By expressing the stored data by the residual polarization of the ferroelectric capacitor, a nonvolatile memory device is realized.
The specification of U.S. Pat. No. 4,873,664 discloses two types of ferroelectric memory device. In a first type, a memory cell is composed of one transistor and one capacitor per bit (1T1C), and a reference memory cell is provided in, for example, every 256 main body memory cells (normal cells). In a second type, without using reference memory cell, a memory cell is composed of two transistors and two capacitors per bit (2T2C), in which a pair of complementary data are stored in a pair of ferroelectric capacitors.
As the ferroelectric material for composing capacitor, KNO.sub.3, PbLa.sub.2 O.sub.3 --ZrO.sub.2 --TiO.sub.2, and PbTiO.sub.3 --PbZrO.sub.3 are known among others. According to PCT International Disclosure No. WO93/12542 Publication, ferroelectric materials extremely small in fatigue as compared with PbTiO.sub.3 --PbZrO.sub.3 suited to ferroelectric memory device are also known.
For example, the constitution of ferroelectric memory device in 2T2C composition and its conventional operation mode are briefly described below. FIG. 31 is a memory cell block diagram, FIG. 32 is a sense amplifier circuit diagram, FIG. 33 is an operation timing chart, FIG. 34 is an operation hysteresis characteristic diagram of ferroelectric capacitor, and FIG. 35 is a relation diagram of supply voltage and bit line voltage when reading out data.
In FIG. 31, C00 to C37 refer to ferroelectric capacitors, CPD is a cell plate driver, SA0 to SA3 are sense amplifiers, CP is a cell plate signal, WL0 to WL3 are word lines, and BL0 to BL3, /BL0 to /BL3 are bit lines. In FIG. 32, BP is a bit line precharge signal, /SAP, SAN are sense amplifier control signals, VSS is a grounding voltage, and VDD is a supply voltage.
In FIG. 34, points A to F refer to hysteresis characteristics when positive and negative electric fields are applied to both electrodes of the ferroelectric capacitor, and points P901 to P903 indicate the reading state of the ferroelectric capacitor.
In the memory cell composition, for example, bit lines BL0 and /BL0 are connected to the sense amplifier SA0, and ferroelectric capacitors C00, C01 are connected to the bit lines BL0 and /BL0 through an N-channel MOS transistor having word line WL0 as its gate. The ferroelectric capacitors C00, C01 are connected to the cell plate signal CP which is driven by the cell plate driver CPD. The sense amplifier SA0 is driven by sense amplifier control signals /SAP, SAN, and the circuit is thus composed so that precharge of bit lines BL0 and /BL0 is controlled by the bit line precharge signal BP.
The operation is further described by referring to FIG. 33 and FIG. 34.
First, the bit lines BL0 and /BL0 are precharged to logic voltage L by the bit line precharge signal BP. Then the bit line precharge signal BP is set to logic voltage L, and the bit lines BL0 and /BL0 come into floating state.
The initial states of the ferroelectric capacitors C00 and C01 are as indicated by point B and point E in FIG. 34, respectively. Consequently, the word line WL0 is set to logic voltage H, and the cell plate signal CP to logic voltage H. Herein, the potential level of the logic voltage H of the word line WL0 is a voltage boosted above the supply voltage VDD. At this time, an electric field is applied to both. electrodes of the ferroelectric capacitors C00 and C01, and potentials determined by the capacity ratio of the capacity of the ferroelectric capacitor and the bit line capaci

REFERENCES:
patent: 4873664 (1989-10-01), Eaton, Jr.
Japanese language search report for Int'l Application No. PCT/JP97/00882.
English translation of Japanese language search report.

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