Data reading circuit for semiconductor memory device

Details Data reading circuit for semiconductor memory device Data reading circuit for semiconductor memory device

1987-01-20

1989-06-27

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

365190, 365207, 3652335, 307530, G11C 700, G11C 1140

Patent

active

048435953

ABSTRACT:
A data reading circuit for a semiconductor memory device includes: a first input terminal and a second input terminal each receiving complementary signals. A first and a second current mirror type sense amplifiers, each including a reference node, an output terminal, a first transistor connected with the reference node, and a second transitor connected with the output terminal. A gate of the first transitor of the first current mirror type sense amplifier and a gate of the second transistor of the second current mirror type sense amplifier are connected to the first input terminal. A gate of the second transistor of the first current mirror type sense amplifier and a gate of the first transitor of the second current mirror type sense amplifier are connected to a second input terminal. The data reading circuit further includes a short-circuiting transistor connected between the reference nodes of both the first and the second current mirror type sense amplifiers. The first short-circuiting transistor is able to conduct therethrough temporarily by receiving a clock signal at a gate.

REFERENCES:
patent: 4570091 (1986-02-01), Yasuda
patent: 4697112 (1987-09-01), Ohtani et al.
patent: 4713797 (1987-12-01), Morton
patent: 4727517 (1988-02-01), Veno
patent: 4742488 (1988-05-01), Wong

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