Data read circuit of semiconductor memory device and method of r

Details Data read circuit of semiconductor memory device and method of r Data read circuit of semiconductor memory device and method of r

1989-10-23

1992-05-19

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365190, G11C 700

Patent

active

051154129

ABSTRACT:
A semiconductor memory device includes a data output bus (I/O, I/O; CD, CD; DB) for transmitting therethrough a read-out potential of a selected one of memory cells (1; MC), and an amplifier circuit (3; 3') for detecting and amplifying a potential on this data output bus. This semiconductor memory device further includes a circuit (Q6, Q7; Q6, Q7, Q12, Q13) for charging the data output bus from a first power supply to a first potential, and a circuit (Q8, Q9, 5; 5', Q8, Q9) for detecting the potential on the data output bus and being activated responsive to shifting of this data output bus potential in the direction of a first supply potential for coupling the data output bus potential to a second power supply to recover the same to the first potential at a high speed. When the data output bus rises in potential above the first potential, the charging circuit does not function, but the recovering circuit functions to recover the potential on this data output bus to the first potential at a high speed by coupling the data input/output bus to a second supply potential. The recovering circuit includes insulated gate type field effect transistors Q8 and Q9 having their gates supplied with a voltage obtained by lowering the first potential further by threshold voltages of these insulated gate type field effect transistors.

REFERENCES:
patent: 4272834 (1981-06-01), Noguchi et al.
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4592021 (1986-05-01), Suzuki et al.
patent: 4670706 (1987-06-01), Tobita

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