Data rate doubler for electrical backplane

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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Details

C710S060000, C713S600000

Reexamination Certificate

active

06269414

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
BACKGROUND OF THE INVENTION
The present invention relates to industrial controllers for the real-time control of industrial processes, and in particular, to an industrial controller having modular components including modular input and output circuits. Industrial controllers are special purpose computers used for controlling industrial processes for manufacturing equipment. Under the direction of a stored program, the industrial controller examines a series of inputs reflecting the status of a controlled process or controlled equipment, and changes outputs effecting control of the process or equipment. In the simplest case, the inputs and outputs are binary, i.e., “ON” or “OFF”; however, analog inputs and outputs taking on a continuous range of values and multiword digital values are also used. The signals received by the industrial controller from the controlled process, and transmitted from the industrial controller to the controlled process, are normally passed through one or more input/output (I/O) modules which serve as electrical interfaces between the controller and the process. In a typical industrial controller, a central computer-like processor communicates with a number of these separate I/O modules, some of which may be spatially remote from the processor and connected to the processor by means of a communication network attached to an adapter which communicates with the I/O modules.
By dividing the function of the industrial controller among the central processor and a number of separate I/O modules, I/O data may be efficiently collected and disseminated at spatially separated points in the controlled process. The use of separate I/O modules also permits the industrial controller to be flexibly configured to meet a given control task without the need to purchase and configure unnecessary I/O modules. Modularity is provided by connecting the various modules to a common backplane which serves to conduct data between the modules. Then additional points of interface between the controller and processor are needed, new I/O modules may be connected to the backplane.
The backplane may transfer data over a number of parallel data conductors as synchronized to a clock signal also on the backplane. Data is placed on the backplane as triggered by a first edge of the clock signal, and after a period of stabilization, read from the backplane on a second edge of the clock signal. The frequency of the clock signal will normally be adjusted to provide greatest data transfer rate commensurate with the limitations in the hardware in writing and reading the data. In such synchronous systems, at any given time, one modular device will have control of the backplane for transmitting data to prevent transmission conflicts.
As new I/O modules are developed having extended functions, pre-existing backplanes may have insufficient capacity to communicate the necessary data at the desired rate. While modification of the backplane to accommodate faster data transmission is possible, for example, by increasing the clock frequency, such modification risks losing compatibility with pre-existing “legacy” modules. Failure to maintain such compatibility makes using a new “extended function” module unattractive to the extent that it may require the customer to replace all legacy hardware. Additional costs may be incurred if rewiring I/O lines to modules replacing the legacy modules, and changing the control program to accommodate the replacement modules is required.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a method of obtaining increased performance from an industrial controller backplane, allowing the backplane to support a higher data transfer rate needed for new modules, while preserving the backplane's compatibility with slower, legacy I/O modules.
Generally, the invention partitions data transmission into first and second periods, the first period being centered around the rising edge of the clock signal as is normally recognized by legacy hardware, and second period being centered around the falling edge of the clock signal. Extended function modules receive data in both the first and second periods, legacy modules receive data only in the first period, as was always the case. In this way, extended function modules may receive data at twice the data rate without affecting the clock rate of the backplane nor the ability of legacy modules to receive data and thus to be compatible with the same backplane. A specific flag bit in the header of messages transmitted on the backplane may distinguish between conventional and extended data, eliminating any ambiguity by the modules.
Specifically, the present invention provides a method of increasing the data capacity of an electrical backplane while maintaining compatibility with legacy modules connected to the electrical backplane, the electrical backplane having a plurality of parallel data lines and a clock line providing a clock signal with a logical rising edge and a logical falling edge, the legacy modules reading data from the backplane at the logical rising edge. The method includes the steps of outputting first data to the data lines at a time between successive logical falling and rising edges, and holding the data on the data lines during a latter logical rising edge for reading by both legacy and extended modules. The method further outputs second data to the data lines at a time between successive logical rising and falling edges, and holds that data on the data lines during a latter logical falling edge for reading by extended modules only.
Thus, it is one object of the invention to allow both high and low data rate modules to be connected to the same electrical backplane originally designed for low data rate modules.
The second data may be transmitted as part of a message of first and second data, the message preceded with a data header identifying it as including second data. Thus, it is another object of the invention to allow dual data rate transmission on a backplane while avoiding possible ambiguity to the receiving modules.
The step of outputting first and second data to the data lines at a time between logical falling and rising edges may involve the step of producing a secondary synchronous clock signal, not transmitted on the backplane, and having twice the frequency of the clock signal, and outputting data at the logical rising edges of the second clock signal.
Thus, it is another object of the invention to allow the high data rate transfer described above while maintaining the reliability and predictability of a synchronous system.
The foregoing and other objects and advantages of the invention will appear from the following description. In this description, reference is made to the accompanying drawings which form a part hereof and in which there is shown by way of illustration a preferred embodiment of the invention. Such embodiment does not necessarily represent the full scope of the invention, however, and reference must be made therefore to the claims for interpreting the scope of the invention.


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Accelerated Graphics Port Interface Specification Revision 1.0 Intel Corporation Jul. 31, 1996.

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