Static information storage and retrieval – Read/write circuit – Signals
Patent
1997-12-23
2000-05-09
Nelms, David
Static information storage and retrieval
Read/write circuit
Signals
36518517, 365184, G11C 700
Patent
active
060612800
ABSTRACT:
An EEPROM chip includes a unit cell array. A plurality of word lines and bit lines are formed on the unit cell array. Unit cells are arranged at the intersections of these lines. Each unit cell is formed of a NAND-type cell including a plurality of memory transistors connected in series between the bit line and the word line. A selection transistor is connected in series between the drain terminal of the NAND-type cell and the bit line. Another selection transistor is connected in series between the source terminal of the NAND-type cell and the word line. In a normal read operation, a voltage of 5 V (power supply voltage Vcc) is applied to a selection gate to turn on the selection transistor. A read reference voltage of 0 V is applied to a control gate of a selected memory transistors. An ON voltage of 5 V is applied to non-selected control gates to turn on the unit cells having the non-selected control gates. In a read-inhibiting operation, a voltage for forcibly turning off the memory transistor is applied to at least one of the non-selected control gates. The voltage for forcibly turning off the memory transistor is, e.g., -5 V. When such a voltage is applied to the control gate, the current path of the NAND-type cell is cut off. Therefore, no data can be read out from the memory transistor.
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Kabushiki Kaisha Toshiba
Le Thong
Nelms David
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