Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-12-23
2001-09-04
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S164000, C710S200000, C713S152000
Reexamination Certificate
active
06286086
ABSTRACT:
TECHNICAL FIELD
This invention relates to a method of protecting data in a semiconductor electronic memory having a memory matrix and respective matrix address decode and pre-decode blocks.
The invention also relates to a semiconductor electronic memory device having a protection function for the data stored therein, and being of a type which comprises a memory matrix and respective matrix address decode and pre-decode blocks.
Semiconductor memories are used in apparatus of ever more sophisticated design and expanding acceptance which require protection for the data stored therein.
The term “protection” may either encompass:
protection from unintentional writing or erasing; or
protection from tampering in order to extract or modify the memory contents.
The invention is particularly, but not exclusively, concerned with the latter type of protection, and the ensuing description will cover this field of application for convenience of explanation.
BACKGROUND OF THE INVENTION
As is known, in semiconductor memories, conditional access must be provided to certain memory portions. An ability to defeat deceptive attempts carried out by reading from the interdicted areas of such memories is of paramount importance. For example, data relating to the protection code CP of the memory would be stored in such areas.
On the other hand, semiconductor memories have other areas where information is stored which can be read and/or modified in the usual manner. Thus, the situation is one where different memory areas may or may not be conceded to reading.
In addition, a semiconductor memory usually includes areas containing program instructions to be executed.
The simplest way of providing a safety feature includes using a decoding code DEC, also known as the access or identification code, which usually comprises a few bytes or memory words. Without this decoding code, no consistent data can be read from the memory, nor can the contents of previously stored data be modified.
Thus, the location Xdec of the decoding code DEC is critical to the achievement of improved safety for a semiconductor memory.
In particular, the location Xdec of the decoding code DEC should meet certain basic requirements, as follows:
it should be a read-only area, or at least an area which is only intelligible to the manufacturer in possession of the decoding code DEC;
it should be an unmodifiable area under any conditions of the memory operation; and
it should be an area readily accessible at the fabrication stage and later on for servicing.
It should be considered, in fact, that the memory write time is a critical parameter at its fabrication stage. In particular, providing easily accessed memories is important if this write time is to be reduced.
A first prior approach to filling this demand includes using some memory locations of unknown address into which the bytes of the protection code CP could be stored. The reliability of this prior method is dependent on two features:
the address at which the protection code CP has been stored is unknown; and
in any event, the data stored at that address cannot be interpreted directly.
However, this first protection method has certain unfavorable features which make it complicated to apply and lower its safety level.
In conventional semiconductor memories, these memory locations for the bytes of the protection code CP can only be provided within a memory array shared with the data. It is, therefore, necessary to use a software program for the write step which can memorize and avoid memory bits already in use.
However, the problem arises of how to erase the whole memory, or whole sections thereof which might contain bytes of the protection code CP. This problem is intensified in the instance of semiconductor memories of the flash type.
In this situation, the erase operation must be preceded by a temporary saving of the memory protection code CP. For the purpose, a temporary or buffer memory may be used from which the protection code CP can later be read for re-writing to the bytes re-assigned thereto.
Consequently, a protection method of that type tends to complicate both the hardware and the software of the semiconductor memory. In particular, the step of copying the protection code CP during the semiconductor memory fabrication process represents an unacceptable waste of time in such applications as cellular phones.
Furthermore, since the bytes of the protection code CP are written and erased using standard commands, anybody would be able to damage or read the protection code CP contained therein, and possibly fully interpret it without the decoding code DEC.
SUMMARY OF THE INVENTION
An embodiment of the invention provides a truly effective data protection method is based on the following considerations:
it is convenient that the address space reserved for the protection code CP is locates outside the memory array into which standard data is written;
the protection code CP can be written only once and cannot be erased;
it is of advantage that different write/read procedures be used which differ, but not to a substantial extent, from standard; in fact, slightly modified write/read procedures would allow a managing software to be used which is basically similar as that used for standard operations.
The embodiment provides a data protection method for semiconductor memories, and a protected memory configuration, which have such structural and functional features as to overcome the drawbacks of prior protection methods and semiconductor memories.
The embodiment is directed to a protection method which utilizes an OTP (One Time Programmable) memory area, and can meet all of the above requirements regarding safety, reliability, and ease of access, for a protected memory configuration in accordance with the method.
Specifically, the embodiment uses a small, suitably configured portion of the standard memory array, and does not require that more than two extra instructions be added to the standard instruction sequence for the memory read/write operations.
The features and advantages of the protection method and memory device according to the invention will be apparent from the following description of a non-limiting embodiment thereof, given with reference to the accompanying drawings.
REFERENCES:
patent: 4744062 (1988-05-01), Nakamura et al.
patent: 5117388 (1992-05-01), Nakano et al.
patent: 5206938 (1993-04-01), Fujioka
patent: 5357573 (1994-10-01), Walters
patent: 5434999 (1995-07-01), Goire et al.
patent: 5619671 (1997-04-01), Bryant et al.
patent: 5691945 (1997-11-01), Liou et al.
patent: 5978915 (1999-11-01), Lisart et al.
Campardo Giovanni
Ghezzi Stefano
Giannini Giuseppe
Torricelli Piero Enrico
Galanthay Theodore E.
Nguyen Hiep T.
Rupnick Charles J.
Seed Intellectual Property Law Group PLLC
STMicroelectronics S.r.l.
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