Data processor with variable types of cache memories

Details Data processor with variable types of cache memories Data processor with variable types of cache memories

1994-07-27

1998-12-08

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, G06F 1208

Patent

active

058484329

ABSTRACT:
A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

REFERENCES:
patent: 5185878 (1993-02-01), Baror et al.
patent: 5226133 (1993-07-01), Taylor et al.
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5404484 (1995-04-01), Schlansker et al.
patent: 5561781 (1996-10-01), Braceras et al.
Hennessy et al., "Computer Architecture A Quantitative Approach," 1990, pp. 460-465.
Intel, "Intel 386 DX Microprocessor Hardware Reference Manual," 1991, p. 7-3 to 7-8 & 7-20 to 7-22.

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