Data processor with hardware accelerator, accelerator...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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C711S154000, C711S148000, C711SE12066

Reexamination Certificate

active

08055872

ABSTRACT:
A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.

REFERENCES:
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patent: 2003/0028751 (2003-02-01), McDonald et al.
patent: 2004/0003204 (2004-01-01), Yamada et al.
Sirowy et al.: “Two-Level Microprocessor-Accelerator Partitioning,” EDAA, Department of Computer Science and Engineering—University of California, Riverside, pp. 313-318, 2007.
Lazanyi: “Instruction Set Extension Using Microblaze Processor,” IEEE 2005, Budapest University of Technology and Economics Department of Measurement and Information Systems, Budapest, pp. 729-730.
Takeuchi et al.: “Scalable Bus Interface for HSDPA Co-processor Extension,” IEEE 2005 Custom Integrated Circuits Conference, pp. 51-54.
Hodjat et al.: “Interfacing a High Speed Crypto Accelerator to an Embedded CPU,” IEEE, pp. 488-492, 2004.

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