Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2008-02-21
2011-11-08
Chery, Mardochee (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000, C711S148000, C711SE12066
Reexamination Certificate
active
08055872
ABSTRACT:
A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.
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Biles Stuart David
Paver Nigel Charles
Sudanthi Chander
ARM Limited
Chery Mardochee
Nixon & Vanderhye P.C.
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