Patent
1995-12-05
1997-03-18
Pan, Daniel H.
395412, 395416, G06F 1206, G06F 1210
Patent
active
056131518
ABSTRACT:
A data processor includes 32 user registers arranged in two banks of 16 registers each. 4-bit addressing is provided. A 16-bit map register determines the bank from which an addressed register is selected. This determination is made individually for each address. The map register is readable and writable so that the mapping of addresses to banks is under program control. This arrangement provides for accessing a large number of registers using a short address code; registers remaining addressable after a remapping retain their addresses.
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