Data processor with changeable architecture

Details Data processor with changeable architecture Data processor with changeable architecture

2007-01-09

2007-01-09

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Mode switch or change

C712S214000, C712S227000

Reexamination Certificate

active

10367097

ABSTRACT:
A program counter having an independent context for each virtual processor is provided, and a non-native instruction fetched from a main memory based on address information generated by the program counter is classified by property by an instruction classifying unit. Then an instruction merge information memory is read out utilizing address information prescribed for each classified group as reference address, and native execution control information is merged and executed. Selection and switching of the virtual processor is performed through selectively switching the instruction classifying unit and an active portion of the instruction merge information memory, and the switching timing is appropriately adjusted by synchronizing with a switching enabling signal output from the instruction merge information memory.

REFERENCES:
patent: 5925124 (1999-07-01), Hilgendorf et al.
patent: 6014735 (2000-01-01), Chennupaty et al.
patent: 6154819 (2000-11-01), Larsen et al.
patent: 6760832 (2004-07-01), Nishimoto et al.
patent: 6917997 (2005-07-01), Bhagat
patent: 2002/0169945 (2002-11-01), Haraguchi

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