Data processor with cache and method of operation

Details Data processor with cache and method of operation Data processor with cache and method of operation

1997-05-02

1998-09-15

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711145, 711146, 39575005, 39575006, G06F 1200

Patent

active

058095322

ABSTRACT:
A data processor (10) has a data cache (16) that supports snooping operations and conserves power. A freeze logic unit (46) enables the data cache when the data cache performs a load/store operation from an execution unit (24) or when it detects a snoop operation. However, the freeze logic unit disables all clock regenerators (44) coupled to the data cache while the data cache waits for data to be returned to it from a common memory system after a data "miss."

REFERENCES:
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5440747 (1995-08-01), Kiuchi
patent: 5555382 (1996-09-01), Thaller et al.
patent: 5557769 (1996-09-01), Bailey et al.
patent: 5603037 (1997-02-01), Aybay
patent: 5623629 (1997-04-01), Suzuki et al.

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