Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-04-08
1998-06-02
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711145, 395586, G06F 1208
Patent
active
057617236
ABSTRACT:
A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.
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Black Bryan P.
Denman Marvin
Kearney Mark A.
Song Seungyoon Peter
Chan Eddie P.
Motorola Inc.
Nguyen Hiep T.
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