Electrical computers and digital processing systems: memory – Address formation – Operand address generation
Patent
1996-06-17
1998-06-09
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Operand address generation
G06F 1200
Patent
active
057652163
ABSTRACT:
A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.
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Anderson Donald C.
Astrachan Paul M.
Curtis Peter C.
Kuenast Walter U.
Weng Chia-Shiann
Lane Jack A.
Motorola Inc.
Polansky Paul J.
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