Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1996-09-20
1998-06-09
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711170, 711 3, 711144, 711145, 711154, 711160, G06F 1200
Patent
active
057651990
ABSTRACT:
A data processor (10) has a cache array (40) and a control unit (58) for storing a number of recently accessed data lines. If an execution unit requests a data line that is not stored in the memory cache (a miss) then the control unit will request the data from an external memory device and allocate a location in the cache array in which it will store the requested data when returned. In the depicted embodiment, the control unit first attempts to allocate an invalid one of N possible locations, where N is the set way associativity of the memory cache. If none of the ways is invalid, then the control unit uses a least recently used (LRU) algorithm to select the location. Therefore, the data cache may be non-blocking up to N times to the same set.
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Chang Joseph Y.
Lioe Hidayat
Reed Paul A.
Snider Brian J.
Chan Eddie P.
Kim Hong C.
Motorola Inc.
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