Data processor which controls interrupts during programming and

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Patent

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Details

711103, G06F 922

Patent

active

058812954

ABSTRACT:
To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

REFERENCES:
patent: 5410711 (1995-04-01), Stewart
patent: 5539890 (1996-07-01), Rahman
patent: 5603038 (1997-02-01), Crump

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