Data processor which accesses a second memory while responding t

Details Data processor which accesses a second memory while responding t Data processor which accesses a second memory while responding t

1999-03-05

2000-10-31

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

710 3, 710266, 710269, 711103, 712 2, G06F 1300, G06F 922

Patent

active

061417009

ABSTRACT:
To obtain a correct vector address even if an interrupt occurs during erasing or programing of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

REFERENCES:
patent: 4872106 (1989-10-01), Slater
patent: 5088023 (1992-02-01), Nakamura et al.
patent: 5093826 (1992-03-01), Leichum
patent: 5163148 (1992-11-01), Walls
patent: 5276839 (1994-01-01), Robb et al.
patent: 5276890 (1994-01-01), Arai
patent: 5410711 (1995-04-01), Stewart
patent: 5506994 (1996-04-01), Sugita
patent: 5539890 (1996-07-01), Rahman
patent: 5603038 (1997-02-01), Crump
patent: 5687345 (1997-11-01), Matsubara et al.
patent: 5881295 (1999-03-01), Iwata

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