Data processor used in a data transfer system which includes a d

Details Data processor used in a data transfer system which includes a d Data processor used in a data transfer system which includes a d

1998-05-12

2000-08-15

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 28, 710 23, 710 18, 711154, G06F 1316

Patent

active

061050822

ABSTRACT:
A processor used in a synchronous data transfer system in which a processor, a direct memory access controller and peripheral devices are connected to a memory via the same bus, includes a detection circuit for detecting whether the processor uses the bus in a forthcoming cycle, and a control circuit having a first terminal for acknowledging a request signal from the direct memory access controller requesting a use of the bus, only when the detection circuit detects that the processor does not use the bus in the forthcoming cycle, wherein the control circuit discards a right to use the bus and outputs a response signal to the direct memory access controller indicating that the processor grants the right to use the bus to the direct memory access controller, when the request signal is acknowledged.

REFERENCES:
patent: 4494193 (1985-01-01), Brahm et al.
patent: 4760521 (1988-07-01), Rewald et al.
patent: 5067075 (1991-11-01), Sugano et al.
patent: 5111424 (1992-05-01), Donaldson et al.
patent: 5455918 (1995-10-01), Fowler et al.
patent: 5574868 (1996-11-01), Marisetty
patent: 5633865 (1997-05-01), Short

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