Data processor testing apparatus and a data processor testing me

Details Data processor testing apparatus and a data processor testing me Data processor testing apparatus and a data processor testing me

1998-02-23

2000-02-29

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

39550005, G06F 1100

Patent

active

060322705

ABSTRACT:
A data processor testing apparatus, in which, in an access instruction executing section, an instruction string to be tested for access to cache memories as an object for execution is previously prepared, access data on a memory is set in an instruction cache memory and operand cache memory according to the instruction string to be tested, and in a BI control section, the access data set as described above is invalidated with the BI signal when the access data set in the operand cache memory is data for an address previously decided as an object for invalidation on the memory, and determination is made by a comparison control section as to whether a result of invalidation is acceptable or not.

REFERENCES:
patent: 5673425 (1997-09-01), Iwashita
patent: 5708594 (1998-01-01), Iwashita et al.
patent: 5748879 (1998-05-01), Kobayashi
patent: 5761521 (1998-06-01), Chilinski et al.
patent: 5838897 (1998-11-01), Bluhm et al.
patent: 5841960 (1998-11-01), Ibusuki et al.

Affiliated with

Also associated with

Rating

Data processor testing apparatus and a data processor testing me does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processor testing apparatus and a data processor testing me, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processor testing apparatus and a data processor testing me will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-693274