Data processor system clock checking system

Details Data processor system clock checking system Data processor system clock checking system

1982-01-25

1984-11-13

Smith, Jerry

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 63, H03L 700, H03L 100

Patent

active

044828195

ABSTRACT:
A central clock signal generator generates a plurality of odd and even clock pulses which are distributed to a plurality of logic and circuit modules by clock signal lines of equal length. The central signal generator also generates a plurality of gate pulses which are supplied to the modules on signal lines which can be different in length from one to another. The gate pulses are wide enough to coincide with the clock pulses with appropriate allowance for skew between the pulses. For each pair of pulses engaged delivered to a module a detection circuit is provided which detects if the gate pulse and the clock pulse begin and end in the proper sequence. If an improper sequence occurs, the information is stored in a scannable latch and a machine stop control is generated. The exact failing module can be traced readily from the information supplied in this manner.

REFERENCES:
patent: 3745472 (1973-07-01), Garth
patent: 3974333 (1976-07-01), May, Jr. et al.
patent: 4163946 (1979-08-01), Alberts
patent: 4185245 (1980-01-01), Fellinger et al.
patent: 4295220 (1981-10-01), Blum
patent: 4419739 (1983-12-01), Blum
IBM Technical Disclosure Bulletin, vol. 9, No. 5, 10/66, p. 473, "Pulse Checking Circuit", to P. J. Veneziano.
IBM Technical Disclosure Bulletin, vol. 7, No. 1, Jun. 1964, pp. 32-33, "Clock Pulse Checking Circuit" to Bearnson, et al.
DIPs Verify Strobe Within Time Window to Robert A. Dougherty, Electronics, Feb. 5, 1976 at 102.

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