Data processor provided with instructions which refer to both ta

Details Data processor provided with instructions which refer to both ta Data processor provided with instructions which refer to both ta

1986-07-02

1990-01-23

Clark, David L.

Boots, shoes, and leggings

G06F 934

Patent

active

048962589

ABSTRACT:
A data processor for execution of tagged data and tagless data has a decoder for discriminating whether the data is tagged or tagless one and in case of a tagged data, separates a tag part and uses the remaining part for address computation. The data processor also comprises a unit for evaluating the tag part and a micro program controller for multi-branching in accordance with the evaluation result of the tag part. The tag evaluating unit includes an extender eliminating part for extracting the tag part from data on a data bus, a plurality of tag part storing registers for storing the tag part from the eliminating part under the control of the micro program controller, and a tag multi-way jump encoder for generating a tag multi-way jump address to feed it to the controller on the basis of the outputs of the registers and a signal from the micro program controller, thereby enabling tag multi-way jump.

REFERENCES:
patent: 4212058 (1980-07-01), Gunawardena
patent: 4241396 (1980-12-01), Mitchell et al.
patent: 4751638 (1988-06-01), Azuma
Tick, E. et al., "Towards a Pipelined Prolog Processor", IEEE, 1984, pp. 29-40.
Ungar, D. et al., "Architecture of SOAR: Smalltalk on a RISC," IEEE, 1984, pp. 188-197.
Moor, D. A., "Architecture of the Symbolics 3600," The 12th Annual Int'l Symposium on Computer Architecture, Jun. 1985, pp. 76-83.

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