Data processor memory circuit

Details Data processor memory circuit Data processor memory circuit

2007-08-21

2007-08-21

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

11526687

ABSTRACT:
A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

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K. Nii et al, “A Low Power SRAM Using Auto-Backgate-Controlled MT-CMOS”Proc. of the International Symposium on Low Power Electronics and Design, 1998, pp. 293-298.
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Silicore Corporation, “SLC1657 8-Bit RISC uC Core” Technical Reference Manual, pp. 1-194.
Synthesizable VHDL source code file representing the TOPLOGIC Entity used in “SLC1657 8-Bit RISC uC Core”.
Synthesizable VHDL source code file representing the STRATSREG Entity used in “SLC1657 8-Bit RISC uC Core”.
Synthesizable VHDL source code file representing the RESETGEN Entity used in “SLC1657 8-Bit RISC uC Core”.
Synthesizable VHDL source code file representing the PROGCNTR Entity used in “SLC1657 8-Bit RISC uC Core”.
Synthesizable VHDL source code file representing the REG12CRN Entity used in “SLC1657 8-Bit RISC uC Core”.

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