Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1999-01-07
2001-07-17
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S600000
Reexamination Certificate
active
06263449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a data processor having a function of performing radio communication, and more particularly to a data processor
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including a signal processor such as a microprocessor, which operates in accordance with clock signals. The invention also relates to a method of controlling a frequency of clock signals in accordance with which a microprocessor operates. The invention further relates to a recording medium readable by a computer, storing a program therein for causing a computer to act as a data processor or carry out a method of controlling a frequency of clock signals in accordance with which a microprocessor operates.
2. Description of the Related Art
A data processor having a function of performing radio communication generally includes a microprocessor for data processing. However, such a data processor is accompanied with a problem that operation clocks in accordance with which a microprocessor operates act as noises to thereby degrade quality of received radio signals. In order to overcome such a problem, Japanese Unexamined Patent Publication No. 7-99680 has suggested a method of decreasing a frequency of operation clocks while a radio signal is being received.
Reduction in a frequency of operation clocks is effective for noise reduction as follows. In general, operation clocks in a microprocessor is in proportion to current consumption. Accordingly, it would be possible to reduce electric power of noises by reducing a frequency of operation clocks to thereby reduce electric power consumption. In addition, reduction in a frequency of operation clocks is further accompanied with reduction in electric power of higher-order harmonics produced by operation clocks. Since the above-mentioned method of switching a frequency of operation clocks is effective for reducing current consumption of a device, the method has been adopted in many mobile communication devices.
However, in the above-mentioned method, a frequency of operation clocks in a microprocessor is always caused to reduce, while a radio signal is being received, regardless of whether quality of a received radio signal is acceptable or not. As a result, even if quality of a received signal is acceptable and noises are sufficiently small, a frequency of operation clocks is reduced, which means that a microprocessor operate at a lower speed.
In addition, if a frequency of operation clocks is reduced, a response speed in response to a user's operation is also reduced. In accordance with the above-mentioned method, reliability in radio communication takes precedence over high-speed operation of a microprocessor while a radio signal is being received, and thus, a user is not allowed to select high-speed operation over reliability in radio communication.
Furthermore, a user cannot notice reduction in a frequency of operation clocks until he or she knows an actual response speed of a microprocessor.
Japanese Unexamined Patent Publication No. 4-122130 has suggested a mobile radio communication device including a controller, a radio transmitting and receiving section, a rechargeable internal power source to be charged through an external power source, and a switch for turning on or off an electrical path between the external power source and the internal power source. The controller closes the switch to thereby cause the external power source to charge the internal power source while the radio transmitting and receiving section is ceased to operate, and opens the switch to thereby separate the external power source from the radio transmitting and receiving section and cause the internal power source to charge the radio transmitting and receiving section while the radio transmitting and receiving section is operating.
In accordance with the above-mentioned mobile radio communication device, it is possible to suppress noises caused by operation clocks transmitted to the controller, while the radio transmitting and receiving section is caused to cease its operation. However, since the controller operates in accordance with operation clocks while the radio transmitting and receiving section is operating, a problem remains unsolved that quality of a received signal is deteriorated due to noises caused by operation clocks transmitted to the controller, while the radio transmitting and receiving section is in operation.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a data processor which is less influenced by noises caused by operation clocks, and can operate at a high speed when quality of a received signal does not degrade.
It is also an object of the present invention to provide a method of controlling a frequency of, clock signals in accordance with which a data processor operates.
It is further an object of the present invention to provide a recording medium readable by a computer, storing a program therein for causing a computer to act as such a data processor as mentioned above or carry out such a method as mentioned above.
In one aspect of the present invention, there is provided a data processor having radio communication function, including (a) a clock generator for selectively generating clock signals having different frequencies, (b) a signal quality analyzer for analyzing quality of a received signal by comparing quality of a received signal to a predetermined threshold level, and (c) a frequency controller for causing the clock signals to have a first frequency when the quality of a received signal is judged not to degrade, and causing the clock signals to have a second frequency when the quality of a received signal is judged to degrade.
For instance, the first frequency may be set equal to an ordinary frequency, and the second frequency may be set equal to a frequency lower than the ordinary frequency.
In accordance with the above-mentioned data processor, when quality of a received signal degrades, a frequency of clock signals is set smaller, which enhances reliability in radio communication. On the other hand, when quality of a received signal does not degrade, a frequency of clock signals is set equal to an ordinary frequency, which ensures both reliability in radio communication and higher operation speed.
It is preferable the data processor having a microprocessor including both the signal quality analyzer and the frequency controller.
The signal quality analyzer may be designed to compare quality of a received signal to N predetermined threshold levels where N is a positive integer equal to two or greater, in which case, the frequency controller switches a frequency of the clock signals among (N+1) frequencies.
The predetermined threshold level may be designed to be variable. Thus, it would be possible to adjust a timing at which a frequency is to be switched, in accordance with a grade of a function of radio communication to be carried out by the data processor. Hence, a frequency of clock signals can be switched to an optimal frequency.
It is preferable that the data processor further includes an annunciator for annunciating that the clock signals are caused to have the second frequency.
The annunciator makes it possible for a user to readily become aware that the data processor is operating at a low speed.
The data processor may further include a prohibitor for prohibiting a frequency of the clock signals from being switched. A user can take precedence operation speed over quality of a received signal, even when quality of a received signal degrades.
The frequency controller may be designed to keep the clock signals to have the first frequency while the prohibitor prohibits a frequency of the clock signals from being switched.
It is preferable that the signal quality analyzer judges that quality of a received signal degrades when an electric field intensity of the received signal is lower than the threshold level successively M times where M is a predetermined positive integer, and judges that quality of a received signal does not deg
Butler Dennis M.
NEC Corporation
Scully Scott Murphy & Presser
LandOfFree
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