Data processor having data bus and instruction fetch bus provide

Details Data processor having data bus and instruction fetch bus provide Data processor having data bus and instruction fetch bus provide

1998-01-05

1999-09-28

Palys, Joseph E.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 37, 714819, G06F 1100

Patent

active

059580747

ABSTRACT:
A data processor has an internal data bus and an instruction fetch bus provided separately from each other. When a data-read operation mode is designated, data stored in an internal read only memory are read out onto both the internal data bus and the instruction fetch bus, and the data on these buses are then subject to an operation by an execution unit to check the coincidence therebetween, the comparison resultant signal being transferred to the outside.

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patent: 5706423 (1998-01-01), Sugimoto

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