Data processor having an output terminal with selectable output

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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Details

326 83, 326 86, H03K 1716, H03K 190175

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active

058595414

ABSTRACT:
A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

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