Data processor having a cache with efficient storage of...

Details Data processor having a cache with efficient storage of... Data processor having a cache with efficient storage of...

2004-07-08

2010-11-02

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S113000, C711S118000, C712S233000, C712S239000, C712S240000

Reexamination Certificate

active

07827355

ABSTRACT:
A data processor (200) includes an instruction cache (220) and a secondary cache (250). The instruction cache (220) has a plurality of cache lines. Each of the plurality of cache lines stores a first plurality of bits (222) corresponding to at least one instruction and a second plurality of bits (224, 226) associated with the execution of the at least one instruction. The secondary cache (250) is coupled to the instruction cache (220) and stores cache lines from the instruction cache (250) by storing the first plurality of bits (222) and a third plurality of bits (255, 257) corresponding to the second plurality of bits (224, 226). The third plurality of bits (255, 257) is fewer in number than the second plurality of bits (224, 226).

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Actions on the Merits by the U.S.P.T.O. as of Feb. 11, 2008, 1 page.

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