Data processor for reducing set-associative cache energy via...

Details Data processor for reducing set-associative cache energy via... Data processor for reducing set-associative cache energy via...

2005-05-24

2005-05-24

Peikari, B. James (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S213000

Reexamination Certificate

active

06898671

ABSTRACT:
The data processor has a set-associative cache memory capable of performing associative operation using tag information for an indexed cache line. The cache memory includes way prediction part for performing a selection of a way based on the prediction in parallel with the associative operation, generation part for generating way selection determining information based on the associative operation using the subsequent access address during a penalty cycle caused by a prediction miss of the way prediction part, and control part for making a way selected for the subsequent access address after the penalty cycle on the basis of the way selection determining information. Since a way to be hit at the subsequent cache access can be predetermined during the preceding penalty cycle, the cumulative number of penalty cycles can be reduced.

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Michael D. Powell et al., “Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping,” Proceedigs of the 34thInternational Symposium on Microarchitecture (2001).

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