Data processor for implementing virtual pages using a cache and

Details Data processor for implementing virtual pages using a cache and Data processor for implementing virtual pages using a cache and

1998-01-14

2000-04-04

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711203, 365 49, G11C 1500

Patent

active

060473541

ABSTRACT:
A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

REFERENCES:
patent: 4395754 (1983-07-01), Feissel
patent: 5133058 (1992-07-01), Jenseu
patent: 5230045 (1993-07-01), Sindhu
patent: 5473348 (1995-12-01), Fujimoto
patent: 5479627 (1995-12-01), Khalidi et al.

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