Data processor decoding trace-worthy event collision matrix...

Details Data processor decoding trace-worthy event collision matrix... Data processor decoding trace-worthy event collision matrix...

2010-02-01

2011-10-18

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

08041998

ABSTRACT:
A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system.

REFERENCES:
patent: 5615357 (1997-03-01), Ball
patent: 2003/0135719 (2003-07-01), DeWitt et al.
patent: 2004/0064685 (2004-04-01), Nguyen et al.
patent: 2006/0069953 (2006-03-01), Lippett et al.

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