Data processor control subsystem

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G06F 900

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active

044007760

ABSTRACT:
An improved data processor control subsystem in which a cycle counter having a plurality of cascade-connected stages also comprises one or more supplemental or dummy stages, which can be selectively inserted or removed from the chain of cascade-connected stages, to alter the number of sub-cycles in an operating cycle, thereby decreasing the complexity of associated decoding circuitry.

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patent: 3611307 (1971-10-01), Podvin
patent: 3614745 (1971-10-01), Podvin
patent: 3962683 (1976-06-01), Brown et al.
patent: 4040021 (1977-08-01), Birchall et al.
patent: 4047245 (1977-09-01), Knipper
Albers, Variable Radix Shift Counter, IBM Technical Disclosure Bulletin, vol. 19, No. 11, Apr. 1977, pp. 4201-4202.
Barton et al, Clock Pulse Stretching Technique, IBM Technical Disclosure Bulletin, vol. 21, No. 8, Jan. 1979, pp. 3218-3219.
Spengler, Clock Circuit, IBM Technical Disclosure Bulletin, vol. 18, No. 3, Aug. 1975, pp. 867-868.

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