Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-04-17
2002-05-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S202000
Reexamination Certificate
active
06393520
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processor with an internal (built-in) memory operable to perform specified data processing operations, such as analytical operations and numerical arithmetic operations, while reading/writing data (including programs such as instructions) from/into the internal memory.
A so-called memory-incorporated data processor, in which a processing unit and an internal memory (a DRAM (dynamic random access memory) in particular) are formed on a single chip, has recently been developed. In such an arrangement, data can be transferred at a considerably high bit rate, because the processing unit and the internal memory can be connected together via a short data bus having a broad bit width. Accordingly, high-speed data processing can be performed while making full use of the performance of the processing unit.
For example, when such a data processor is applied to a video controller, the internal memory may be used as a frame buffer for video. The video data stored in the frame buffer can be processed at high speed in the processing unit and then supplied through a D/A (digital-to-analog) converter to an external monitor. This makes it possible to provide smooth video images.
In some applications of the data processor, however, required storage capacity cannot be obtained by the internal memory alone. For instance, if the number of colors or the size of a monitor is increased in image processing applications, then the internal memory alone cannot provide sufficient storage capacity for constructing a frame buffer. As an imaginable solution, an internal memory having a relatively great storage capacity may be mounted beforehand in order to cope with various cases. However, such a solution is not cost-effective. Thus, in such a case, an external memory is optionally added, thereby obtaining a desired storage capacity by using the internal and external memories in combination.
However, if such an external memory is added, then a memory system is made up of the internal and the external memories. Thus, the overall performance of the memory system is determined by the access rate of the external memory after all. Although the internal memory is provided, it is hard to improve the overall performance, resulting in several problems. For example, in image processing applications, video image rendering rate becomes adversely low and motions of the image become undesirably awkward.
SUMMARY OF THE INVENTION
The objective of the present invention is providing a data processor, incorporating an internal memory allowing for the improvement of overall memory system performance, for a memory system made up of an internal memory and an external memory having an operating speed lower than that of the internal memory.
In order to solve the above-described problem of the prior art techniques, the present invention provides an improved data processor. In the data processor of the present invention, a memory control unit for performing read/write operations on an external memory and a buffer part for storing data from an internal memory or from the external memory are controllably coupled to a processing unit, thereby carrying out data exchange between the internal memory and the external memory by temporarily storing, in the buffer part, data from the internal memory or from the external memory.
In the data processor of the present invention, either data obtained from the external memory through the memory control unit or data obtained from the internal memory is temporarily stored in the buffer part, and physical data exchange can be carried out between the internal memory and the external memory. Thus, it is possible to store data requiring fast processing in the internal memory and data not requiring so fast processing in the external memory, respectively. As a result, the overall memory system performance can be improved when degrees of necessity of high speed processing are variable among access areas (memory regions) of a memory system. In general, in the case of transferring data between an external memory (main memory) and an internal memory (cache memory), data in the internal memory is copied to the external memory without applying any modification thereto. Also, even in the case of swapping data between an internal memory (main memory) and an external memory (a magnetic disk device) in a virtual memory system, data in the internal memory is also copied to the external memory without applying any modification thereto. In other words, in both of these cases, a region corresponding to the internal memory always exists in the external memory. However, in the data processor of the present invention, no such regions corresponding to the internal memory exist in the external memory. Therefore, a sum of the storage capacity of the external memory and that of the internal memory can be used as a memory space without wasting any memory region.
The present invention is also characterized in that the processing unit includes an address management part for controlling addresses of said internal and external memories. When data exchange is performed between said internal memory and the external memory, address allocations corresponding to the data exchange are exchanged by the address management part. Thus, even if data has been exchanged between arbitrary physical addresses, the logical addresses remain unchanged in spite of such data exchange. Therefore, it is not necessary to reform a logical memory map of the memory system.
In one embodiment of the present invention, the memory control unit may be provided with an additional function of performing data conversion in parallel or in series between the internal memory and the external memory. And the processing unit and the memory control unit may be coupled together via a data bus having the same width as a width of a data bus between the internal memory and the processing unit. In such arrangement, the processing unit need not convert data, provided from the internal memory through a data bus having a width and coupling the processing unit to the internal memory, into data corresponding to a width of a data bus between the processing unit and the memory control unit, in order to output the data to the memory control unit. As a result, the load of the processing unit can be lightened, and a data bus having the same width can be used in common between the processing unit and the internal memory and between the processing unit and the memory control unit.
In another embodiment of the present invention, the memory control unit or the processing unit may be provided with a comparator for comparing a data item from the internal memory with another data item from the external memory. If the comparator indicates that these data items are different from each other, the data items may be written into the internal memory or into the external memory, thereby exchanging the data items between the internal memory and the external memory. In such an arrangement, if the comparator indicates that these items are the same, a write cycle need not be activated with respect to the internal and external memories. Thus, the processing load and time required for performing data exchange can be reduced.
In still another embodiment, the memory control unit or the processing unit may be provided with an arithmetic part for performing data arithmetic operations on the data from the internal and external memories. For example, if the data processor of the invention is applied to an MPEG (moving picture experts group) encoder and I/B/P pictures stored in the internal memory and in the external memory are different from each other, it is possible to perform inter-picture data arithmetic operations when data is exchanged between the internal memory and the external memory. As a result, it is possible to store post-arithmetic picture data in at least one of the memories during the data exchange.
In still another embodiment, the data exchange may be carried out with respect to a memory region having a specified storage capacity
Akamatsu Hironori
Takahashi Satoshi
Yoshikawa Takefumi
Kim Matthew
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Tran Denise
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