Data processor and data processing system having two translation

Details Data processor and data processing system having two translation Data processor and data processing system having two translation

1997-10-15

2000-07-18

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711203, 711205, 711206, G06F 1200, G06F 1300

Patent

active

060921722

ABSTRACT:
A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

REFERENCES:
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patent: 5627992 (1997-05-01), Baror
patent: 5712998 (1998-01-01), Rosen
patent: 5737590 (1998-04-01), Hara
patent: 5752275 (1998-05-01), Hammond
patent: 5784708 (1998-07-01), Bridges et al.
Power PC 603 RISC Microprocessor User's Manual, Motorola, 1994, pp. 7.1-7.19.

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