Data processor and data processing method reduced in power...

Details Data processor and data processing method reduced in power... Data processor and data processing method reduced in power...

2005-07-12

2005-07-12

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S105000, C711S108000, C711S111000, C365S226000, C365S227000, C365S228000, C365S229000

Reexamination Certificate

active

06918002

ABSTRACT:
When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

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“Mitsubishi Semiconductor data book 1997 Memory SRAM” Mitsubishi Denki Kabushiki Kaisha, pp. 2-9, 2-15.

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