Electrical computers and digital data processing systems: input/ – Input/output data processing – Frame forming
Reexamination Certificate
2001-03-21
2004-05-11
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Frame forming
C710S071000, C370S465000, C370S474000
Reexamination Certificate
active
06735644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data processing apparatus and a data processing method used for high-speed serial communications.
2. Description of the Related Art
One of the global standards for realizing high-speed data communications is the SDH (Synchronous Digital Hierarchy). The SDH specifies the synchronous transfer mode called STM (Synchronous Transfer Mode). The bit rate of the corresponding module STM-1 (Synchronous Transport Module Level One) is 155.52 Mb/s.
The frame structure of the STM-1 is composed of a byte matrix of nine rows by 270 columns. The leading section of nine rows by one column is called the section overhead (hereinafter referred to as the SOH). The subsequent section of nine rows by nine columns is called the payload. The SOH is a management section having frame synchronization signals and maintenance information appended to the payload. The payload accommodates multiplexed real data.
In the STM, one frame is transmitted in 125 microseconds. Bit rate depends on the number of bytes corresponding to the data of one row by one column. For example, in the STM-1, data of one row by one column is one-byte data thus nine rows×270 bytes×(1/125 microseconds)=155.52. The bite rate is 155.52 Mbps. The SDH specifies standardized modules such as the STM-4 having a bit rate four times as large as that of the STM-1, with the data of one row by one column being four bytes, and the STM-16 having a bit rate 16 times as large as that of the STM-1, with the data of one row by one column being 16 bytes.
The STM divides one frame into a plurality of time slots (channels) and multiplexes a plurality of data pieces by storing in each time slot original data such as user data that is transmitted/received. Such multiplexed data is transmitted as serial data via the SDH transmission network.
In the data transmitted via the SDH transmission network is inserted predetermined data (idle data) in order to delimit data in the STM. In order to distinguish original data having the sane code as idle data, predetermined data conversion is performed. Thus, it is necessary for the receiving party to perform transparent processing for restoring data converted by the sending party.
The transparent processing is a processing whereby received serial data is sequentially converted to parallel data every eight bits and predetermined data (transparent data) converted at the sending party is converted (restored) to original data at the receiving party of the SDH transmission network.
FIG. 4
is a schematic diagram of the transparent processing according to the related art.
In
FIG. 4
, received serial data is input to a transparent data detector
110
of a data processor
100
. The transparent data detector detects information on the transparent data in the received data such as the position of the transparent data and sends the received data and detected information to a transparent data converter
120
. The transparent data converter
120
converts the transparent data in the received data to the predetermined original data based on the detected information received.
In recent years, high-speed data communications based on the STM-16 are in use with the expansion of communication data.
In the STM-16, parallel conversion on a per eight bits basis requires processing at 311 Mbps (8-bit parallel data processing).
The processing speed of a device used for transparent processing cannot reach 311 Mbps (8-bit parallel data processing).
SUMMARY OF THE INVENTION
An object of the invention is to easily realize the transparent processing on high-speed serial data that is based on the STM.
To achieve the above object, according to a first aspect of the invention, there is provided a data processor used for high-speed serial data communications, comprising:
a data converter (for example an interface provided in a transparent information detector
10
in
FIG. 1
) for receiving high-speed serial data and converting the data to parallel data of predetermined data width;
a transparent data information detector (for example, a transparent information detector
10
in
FIG. 1
) for detecting information on transparent data from the parallel data converted by the data converter;
a data movement controller (for example a pointer controller in
FIG. 1
) for calculating the quantity of data to be moved from parallel data in the subsequent stage based on the transparent data information, the quantity of data decreased by conversion of the transparent data; and
a transparent processor (for example transparent processors
30
a
-
30
e
) for converting transparent data in the parallel data based on the transparent data information and the quantity of data to be moved, moving predetermined data from parallel data in the subsequent stage, and rearranging the moved data into parallel data of predetermined width.
According to the first aspect of the invention, in the data processor used for high-speed serial data communications, the data converter receives high-speed serial data and converts the data to parallel data of predetermined data width, the transparent data information detector detects information on transparent data from the parallel data converted by the data converter, the data movement controller calculates the quantity of data to be moved from parallel data in the subsequent stage based on the transparent data information, the quantity of data decreased by conversion of the transparent data, and the transparent processor converts transparent data in the parallel data based on the transparent data information and the quantity of data to be moved, moves predetermined data from parallel data in the subsequent stage, and rearranges the moved data into parallel data of predetermined width.
According to a fifth aspect of the invention, there is provided a data processing method for data associated with high-speed serial communications, comprising:
a data converting step for receiving high-speed serial data and converting the data to parallel data of predetermined data width;
a transparent data information detecting step for detecting information on transparent data from the parallel data converted by the data converter;
a data calculating step for calculating the quantity of data to be moved from parallel data in the subsequent stage based on the transparent data information, the quantity of data decreased by conversion of the transparent data; and
a transparent processing step for converting transparent data in the parallel data based on the transparent data information and the quantity of data to be moved, moving predetermined data from parallel data in the subsequent stage, and rearranging the moved data into parallel data of predetermined width.
Thus, received serial data can be converted to parallel data and processed based on the detected transparent data information according to the first and fifth aspects of the invention. This allows high-speed serial data to be applied transparent processing via a relatively low-speed device. It is possible to flexibly support serial data of a variety of data speeds by changing as required the data width of parallel data to be converted depending on the speed of the received serial data.
According to a second aspect of the invention, there is provided a data processor according to the first aspect of the invention, wherein the transparent data information detector comprises:
a transparent data detector (for example, a transparent data detector
11
in
FIG. 1
) for detecting the position of transparent data contained in the parallel data converted by the data converter; and
a transparent information sender (for example a transparent information sender
12
in
FIG. 1
) for sending the position of transparent data detected by the transparent data detector to the data movement controller and the transparent processor as the transparent data information.
According to the second aspect of the invention, in a data processor according to the first aspect of the invention, in the transparent data informati
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Huynh Kim
LandOfFree
Data processor and data processing method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processor and data processing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processor and data processing method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3230505