Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2001-03-27
2004-01-13
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S071000, C370S513000
Reexamination Certificate
active
06678762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data processing apparatus and a data processing method used for high-speed serial communications.
2. Description of the Related Art
One of the global standards for realizing high-speed data communications is the SDH (Synchronous Digital Hierarchy). The SDH specifies the synchronous transfer mode called STM (Synchronous Transfer Module). The bit rate of the corresponding module STM-1 (Synchronous Transfer Module Level One) is 155.52 Mb/s.
The frame structure of the STM-1 is composed of a byte matrix of nine rows by 270 columns. The leading section of nine rows by one column is called the section overhead (hereinafter referred to as the SOH). The subsequent section of nine rows by nine columns is called the payload. The SOH is a management section having frame synchronization signals and maintenance information appended to the payload. The payload accommodates multiplexed real data.
In the STM, one frame is transmitted in 125 microseconds. Bit rate depends on the number of bytes corresponding to the data of one row by one column. For example, in the STM-1, data of one row by one column is one-byte data thus nine rows×270 bytes×(1/125 microseconds)=155.52. The bit rate is 155.52 Mbps. The SDH specifies standardized modules such as the STM-4 having a bit rate four times as large as that of the STM-1, with the data of one row by one column being four bytes, and the STM-16 having a bit rate 16 times as large as that of the STM-1, with the data of one row by one column being 16 bytes.
The STM divides one frame into a plurality of time slots (channels) and multiplexes a plurality of data pieces by storing in each time slot original data such as user data that is transmitted/received. Such multiplexed data is transmitted as serial data via the SDH transparence network.
In the data transmitted via the SDH transparence network is inserted predetermined data (idle data) in order to delimit data in the STM. In order to distinguish original data having the same code as idle data, predetermined data conversion is performed. Thus, it is necessary for the receiving party to perform transparence processing for restoring data converted by the sending party.
The transparence processing is a processing whereby received serial data is sequentially converted to parallel data every eight bits and predetermined data (transparence data) converted at the sending party is converted (restored) to original data at the receiving party of the SDH transparence network.
FIG. 9
is a schematic diagram of the transparence processing according to the related art.
In
FIG. 9
, received serial data is input to a transparence data detector
110
of a data processor
100
. The transparence data detector detects information on the transparence data in the received data such as the position of the transparence data and sends the received data and detected information to a transparence data converter
120
. The transparence data converter
120
converts the transparence data in the received data to the predetermined original data based on the detected information received.
In recent years, high-speed data communications based on the STM-16 are in use with the expansion of communication data.
In the STM-16, parallel conversion on a per eight bits basis requires processing at 311 Mbps (8-bit parallel data processing).
The processing speed of a device used for transparence processing cannot reach 311 Mbps (8-bit parallel data processing).
SUMMARY OF THE INVENTION
An object of the invention is to easily realize the transparence processing on high-speed serial data that is based on the STM.
To achieve the above object, according to a first aspect of the invention, there is provided a data processor used for high-speed serial data communications, comprising:
a data converter such as an interface (not shown) provided at the input of a data processor
1
for receiving high-speed serial data and converting the data to parallel data of predetermined data width;
a transparence data information detector (for example, a transparence information detector
20
in
FIG. 1
) for detecting information on transparence data from the parallel data converted by the data converter;
a transparence data converter (for example a transparence data sampling section
30
in
FIG. 1
) for converting transparence data in the parallel data based on the information on transparence data and moving the data toward the head address and rearranging the data within the parallel data; and
a data arrangement section (for example a data arrangement section
40
in
FIG. 1
) for moving predetermined number of data pieces from parallel data in the subsequent parallel data to the rearranged parallel data in the transparence data converter and rearranging the data into parallel data of predetermined data width.
According to the first aspect of the invention, in the data processor used for high-speed serial data communications, the data converter receives high-speed serial data and converts the data to parallel data of predetermined data width, the transparence data converter converts transparence data in the parallel data based on information on the transparence data and moves the data toward the head address and rearranges the data within the parallel data, and a data arrangement section moves predetermined number of data pieces from parallel data in the subsequent parallel data to the rearranged parallel data in the transparence data converter and rearranges the data into parallel data of predetermined data width.
According to a fifth aspect of the invention, there is provided a data processing method for data associated with high-speed serial communications, said method comprising:
a first step for receiving high-speed serial data and converting the data to parallel data of predetermined data width;
a second step for detecting information on transparence data from the parallel data converted by the data converter;
a third step for converting transparence data in the parallel data based on information on the transparence data and moving the data toward the head address and rearranging the data within the parallel data; and
a fourth step for moving predetermined number of data pieces from parallel data in the subsequent parallel data to the rearranged parallel data and rearranging the data into parallel data of predetermined data width.
Thus, received serial data can be converted to parallel data and processed based on the detected transparence data information according to the first and fifth aspects of the invention. This allows high-speed serial data to be applied transparence processing via a relatively low-speed device. It is possible to flexibly support serial data of a variety of data speeds by changing as required the data width of parallel data to be converted depending on the speed of the received serial data.
The transparence data information detector, transparence data converter and data arrangement section can implement their features via relatively simple circuits. This allows scale-down of the overall apparatus and reduction in costs.
According to a second aspect of the invention, there is provided a data processor according to the first aspect of the invention, in which the transparence data information detector comprises:
a storage section for storing parallel data input from the data converter (for example F/F
21
in FIG.
1
);
wherein the transparence data information detector detects information on transparence data concerning the data at the tail address of the stored parallel data and the head address of the subsequent parallel data to be input.
According to the second aspect of the invention, in a data processor according to the first aspect of the invention, a storage section stores parallel data input from the data converter and the transparence data information detector detects information on transparence data concerning the data at the tail address of the stored parallel data and the head address of the subsequent parallel data to
Kondo Hiroyasu
Mori Kenjiro
Ando Electric Co. Ltd.
Fish & Richardson P.C.
Huynh Kim
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