Data processor

Details Data processor Data processor

1999-01-12

2001-11-27

Etienne, Ario (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S120000, C326S030000

Reexamination Certificate

active

06324615

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a data processor having bus lines whereby data exchange is commonly performed among a plurality of inner circuits.
In a conventional data processor having such bus lines, a three-state buffer, which outputs high-impedance output states other than HIGH and LOW logical states, is provided for each of the inner circuits, and only one of the three-state buffer is permitted to exclusively drive the bus lines so that output data of more than one inner circuits may not collide on the bus lines.
FIG. 5
is a block diagram illustrating a partial configuration of a conventional data processor around the bus lines, wherein inner circuits of the data processor, such as an instruction processor, an instruction fetch unit, a cache memory or a main memory, are represented by inner circuts
11
to
15
connected to the bus lines.
In each of the inner circuits
11
to
15
, a three-state buffer is provided, which connects output data of respective one of the inner circuits
11
to
15
to the bus lines time-divisionally, controlled with an output enable signal which is generated according to active status of a bus-usage permission signal supplied to the respective inner circuit from a bus controller
6
for permitting exclusive usage of the bus lines. The output data connected to the bus lines is supplied directly to every of the inner circuits
11
to
15
trough the bus lines.
The bus controller
6
takes charge of arbitrating usage of the bus lines according to bus-usage request signals received from the inner circuits
11
to
15
and enables one of bus-usage permission signals each connected to each of the inner circuits
11
to
15
, respectively.
Each of the inner circuits
11
to
15
controls its three-state buffer by way of the output enable signal generated according to the bus-usage permission signal delivered from the bus controller
6
, and the three-state buffer of the inner circuit whereof the bus-usage permission signal is enabled drives the bus lines of 32 signal lines, for example, exclusively. Thus, data exchange among the inner circuits
11
to
15
is performed commonly, making use of the bus lines.
However, in the conventional data processor, every one of the bus lines must be wired so as to connect with the three-state buffer of every one of the inner circuits. Therefore, the bus lines become inevitably long and their parasitic capacitance becomes large when the number of the inner circuits increases. The wiring widths are very narrow in the highly integrated circuit. Hence, the long bus lines bring high wiring resistance, which becomes a factor of transmission delay of the data exchanged by way of the bus lines, obstructing high-speed data transmission even when the bus lines are driven by transistors of high fan-out ability.
Furthermore, the outputs of every of the three-state buffers are directly connected to the bus lines, in the conventional data processor. Therefore, there may arise an overlap of different outputs from different three-state buffers, resulting in dissipation of useless current.
Still further, a pull-up or a pull-down circuit must be provided to each of the bus lines, for preventing them from being left floating when no three-state buffer drives the bus lines. Otherwise, the high-impedance of the bus lines may cause through current flowing through input gates of the three-state buffers.
SUMMARY OF THE INVENTION
Therefore, a primary object of the present invention is to provide a data processor having a bus means whereby high-speed data exchange can be performed stably without dissipation of useless current, by resolving above problems of the conventional data processor.
In order to achieve the object, a data processor according to the invention has a bus means whereby data exchange among a plurality of inner circuits is commonly performed. The bus means comprises more than one bus selectors cascade-connected into a loop by way of bus lines. Each of the bus selectors outputs bus data supplied from a preceding bus selector as bus data to be supplied towards a following bus selector when none of the inner circuits connected to the bus selector enables an output enable signal, and outputting output data of one of the inner circuits connected to the bus selector as the bus data to be supplied towards the following bus selector when the inner circuit enables the output enable signal.
Each of the bus selectors comprises:
a pre-selector for selecting output data of one of the inner circuits connected to the bus selector when the inner circuit enables the output enable signal; and
a selector for outputting the bus data supplied from the preceding bus selectors as the bus data to be supplied towards the following bus selectors when none of the inner circuits connected to the bus selector enables the output enable signal, and outputting the output data selected by the pre-selector when the inner circuit connected to the bus selector enables the output enable signal.
Therefore, the bus lines can be divided into short sections each driven by a bus selector, and the effect of the wiring resistance of the bus lines to the transmission delay of the bus data can be reduced compared to the conventional data processor.
Furthermore, each section of the bus lines is sufficient to connect each neighboring two bus selectors directly. Therefore, when the number of inner circuits is large, total wiring length of the bus lines can be shortened compared to the bus lines of the conventional data processor which should be connected to the three-state buffer of every of the inner circuits. Hence, wiring resistance and parasitic capacitance of a data path connecting the inner circuits can be reduced, enabling high-speed transmission of the bus data, as well as a compact and a small space layout of the integrated circuit.


REFERENCES:
patent: 3932841 (1976-01-01), Deerfield et al.
patent: 4-131955 (1992-05-01), None
patent: 4-344987 (1992-12-01), None
patent: 6-152618 (1994-05-01), None
patent: 6-236345 (1994-08-01), None
patent: 7-21113 (1995-01-01), None
patent: 9-288640 (1997-11-01), None

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