Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
Patent
1998-07-10
1999-10-26
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to generate an address of a microroutine
712207, 711125, 710127, 710125, G06F 934, G06F 1202
Patent
active
059745339
ABSTRACT:
A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
REFERENCES:
patent: 4439829 (1984-03-01), Tsiang
patent: 4442488 (1984-04-01), Hall
patent: 4646233 (1987-02-01), Weatherford et al.
Hanawa Makoto
Hasegawa Atsushi
Kawasaki Ikuya
Nishimukai Tadahiko
Uchiyama Kunio
Hitachi , Ltd.
Hitachi Micro Computer Engineering Ltd.
Pan Daniel H.
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