Data processing with self-timed feature and low power transition

Details Data processing with self-timed feature and low power transition Data processing with self-timed feature and low power transition

1996-08-01

1997-12-16

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 21, H03K 19096

Patent

active

056989962

ABSTRACT:
A technique is provided for signaling to a first data processing circuit that an output of a second data processing circuit is ready for processing by the first data processing circuit. An occurrence of a logic transition at an input of the second data processing circuit is detected, and a latch circuit is used to produce a detection signal indicative of the occurrence. In response to the logic transition, the output of the second data processing circuit is produced, and this output is provided to the first data processing circuit. In response to production of the detection signal, and after delaying for an amount of time adequate to permit the second data processing circuit to produce its output, a done signal is sent to the first data processing circuit.

REFERENCES:
patent: 3925652 (1975-12-01), Miller
patent: 4039858 (1977-08-01), Stewart
patent: 4692635 (1987-09-01), Rapp
patent: 4775840 (1988-10-01), Ohmori et al.
patent: 4940904 (1990-07-01), Lin
patent: 5121003 (1992-06-01), Williams
patent: 5124584 (1992-06-01), McClure
patent: 5194768 (1993-03-01), Lozano
A. De Gloria, et al., "Delay insensitive mirco-pipelined combinational logic". Microprocessing and Microprogramming, vol. 36, No. 5, 1 Oct. 193, pp. 225-241.
M. A. Franklin, et al., "Clocked and Asynchronous Instruction Pipelines", Processings of the 26th Annual Inernational Symposium on Microarchitecture, 1-3 Dec. 1993, Austin, Texas, pp. 17-184.
John Compton and Alexander Albicki, "Self-Timed Pipeline with Adder," Dept. of Electrical Engineering, University of Rochester, IEEE 1992, pp. 109-113.
Y.K. Tan and Y.C. Lim, "Self-Timed Precharge Latch," Electrical Engineering Dept., National University of Singapore, Kent Ridge, Singapore 0511, 1990 IEEE, pp. 566-569.
Gordon M. Jacobs and Robert W. Brodersen, "A Fully Asynchronous Digital Signal Processor Using Self-Timed Circuits," IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1526-1536.
Ted E. Williams, "Analying and Improving Latency and Throughput in Self-Timed Pipelines and Rings," HaL Computer Systems, Stanford University, pp. 1-10, IEEE 1992.

Affiliated with

Also associated with

Rating

Data processing with self-timed feature and low power transition does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data processing with self-timed feature and low power transition, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing with self-timed feature and low power transition will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-210603