Data processing with a self-timed approach to spurious transitio

Details Data processing with a self-timed approach to spurious transitio Data processing with a self-timed approach to spurious transitio

1994-08-11

1995-12-12

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

326 83, 3652335, 327387, H03K 19003

Patent

active

054753201

ABSTRACT:
A digital electronic device includes a digital circuit responsive to a logic transition at an input thereof to produce at an output thereof a spurious logic transition ultimately followed by a stable logic level. A transition detector produces a detection signal in response to the logic transition at the digital circuit input, the transition detector including a latch circuit having an output for producing the detection signal. A self-timed circuit receives the detection signal and, after delaying for a suitable time, produces a done signal. A switching circuit is responsive to the done signal to connect the digital circuit output to a selected logic node.

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John Compton and Alexander Albicki, "Self-Timed Pipeline with Adder," Dept. of Electrical Engineering, University of Rochester, IEEE 1992, pp. 109-113.
Y. K. Tan and Y. C. Lim, "Self-Timed Precharge Latch," Electrical Engineering Dept., National University of Singapore, Kent Ridge, Singapore 0511, 1990 IEEE, pp. 566-569.
Gordon M. Jacobs and Robert W. Brodersen, "A Fully Asynchronous Digital Signal Processor Using Self-Timed Circuits," IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1526-1536.

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