Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1997-09-12
2001-07-10
Niebling, John F. (Department: 2812)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S224000
Reexamination Certificate
active
06260137
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processing unit and, in particular, to a central processing unit (CPU) such as a microcomputer or microcontroller. Microcontrollers are well known in the art, and a large variety of such devices from low end devices (e.g., a 4/8-bit controller) to high end devices (e.g., a 32-bit controller) are available. Generally microprocessors are divided into two groups, namely general purpose processors, such as complex instruction set computers (CISC) or reduced instruction set computers (RISC), and special microprocessors designed for special purposes, such as digital signal processing processors (DSP).
RISC and CISC processors are usually processors having a plurality of registers or a register file and a single memory of any kind and size and therefore designed to process any kind of data. RISC and CISC processors are not limited for extensions but lack the high speed processing of DSP processors.
DSP processors usually have accumulators and a special memory limited in size. They are designed to calculate data very fast and precise, for example to process sampled signals. The memory is often split into a X-memory and a Y-memory to allow access to two different data in one cycle. This results in totally non orthogonal operations, severe restrictions on addressing modes and such a memory model is definitely not compiler friendly. If specific data is in the “wrong” memory, it has to loaded from X-memory to Y-memory or vice versa. The lack of a register file makes it also difficult to program such a processor in “C”. Furthermore the narrow fixed instruction width makes it impossible to extend such an architecture.
Other systems use coprocessors to speed up operation. These coprocessors do not share any register of the main central processing unit (CPU). Thus, registers of the coprocessor have to be loaded by the CPU, which slows down operation speed significantly and limits usage of registers.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a data processor with DSP features and the versatility of CISC and RISC processors without the need of a coprocessor.
This object is accomplished by a Data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with said single memory. The register file at least two sets of registers whereby the first set of registers can be coupled with one of the word lines and the second set of registers can be coupled with the respective other word lines, a load and store control unit for transferring data from or to the memory.
In one embodiment, the load and store control unit has means to load or store two consecutive words in parallel from or to said memory to or from the first and second set of registers. In another embodiment, one word from the memory can be split into two half-words which are then stored in a first register from the first set of registers and in a second register from the second set of registers. The half-words can be stored into one half of a register and the other half of the register can be filled up with zeros or sign-filled.
In a further embodiment the bus has a plurality of word lines to form a plurality-word wide bus and the register file has a plurality of sets of registers whereby each set of registers is coupled with one of word lines of said plurality of word lines. For example, in a 64 bit data processing unit, two 32 bit half-words or four 16 quarter-words can be accessed during one single cycle. The load and store control unit of the data processing can therefore have means to load or store a plurality of consecutive words in parallel from or to said memory to or from said plurality of sets of registers. These means allow to couple any register of any set of registers with any location within the memory.
In a further embodiment the load and store control unit of the data processing unit can have means to load one word from said memory and to split it into a plurality of partial-words, each partial word is stored in one of said registers of each set of registers, respectively.
A data handling unit according to the present invention has the benefit of using a standard register file with data and address register. Thus an address register can be used, for example as a stack pointer which allows unlimited stack size, whereby digital signal processors often only comprise a hardware stack which is limited in size. “C”-Code can be translated easily into machine code, allowing orthogonal operations with all registers. No constant movement of an accumulator to the memory is necessary as it is for digital signal processors. As registers can be reused, this results also in lower power consumption.
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Fleck Rod G.
Martin Daniel
Niebling John F.
Siemens Aktiengesellschaft
Whitmore Stacy
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