Data-processing unit with a circuit arrangement for...

Details Data-processing unit with a circuit arrangement for... Data-processing unit with a circuit arrangement for...

2005-05-31

2005-05-31

Myers, Paul R. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S309000, C710S312000

Reexamination Certificate

active

06901472

ABSTRACT:
A data processing configuration with a first circuit configuration (1) that connects a first communication bus (2) with a second communication bus (3). The first circuit configuration (1) is the bus master of the first communication bus (2). Furthermore, a second circuit configuration (4) is connected with the first communication bus (2). By employing a wait signal (11), which is generated in the second circuit configuration (4) and transmitted to the first circuit configuration (1), it is possible to expand read and write access to the first communication bus (2) to any random number of clock cycles.

REFERENCES:
patent: 5572706 (1996-11-01), Matsumoto
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5838995 (1998-11-01), Chen et al.
patent: 5978859 (1999-11-01), Sademaa
patent: 6070215 (2000-05-01), Deschepper et al.
patent: 6519670 (2003-02-01), Meiyappan
patent: 6529980 (2003-03-01), Abramson

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