Data processing unit and bus arbitration unit

Details Data processing unit and bus arbitration unit Data processing unit and bus arbitration unit

2011-03-15

2011-03-15

Misiura, Brian T (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S036000, C710S110000, C710S114000, C710S241000, C710S244000, C709S209000, C700S003000

Reexamination Certificate

active

07908416

ABSTRACT:
An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine155grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine155can set an optimal number of bus cycles.

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